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Xilinx ISE and Verilog $signed/$unsigned tasks?

Started by actela September 23, 2004
In ISE Webpack 6.2i, XST (Xilinx Synthesis Technology)
supports Verilog-2001 signed operators and datatypes.
However, for some reason, it doesn't support $signed and
$unsigned.

I mention this, because I frequently use the $signed
and $unsigned calls to explicitly force type-conversion.

I know the Verilog simulator/compiler doesn't care,
but I use $signed/$unsigned for documentation and
code-readability purposes...(did this guy accidentally
  or intentionally transfer a signed -> unsigned?!?)

(as long as the bitwidths don't change ... otherwise
  you have to be careful about the sign-extension!)

output [16:0] unsigned_y;

wire signed [15:0] x, y;
wire signed [16:0] sum;
wire [16:0] sum;

assign sum = x + y; // 2's complement addition!

assign unsigned_y = $unsigned(sum); // type-cast!

......

The problem is that ISE 6.2i doesn't support the
$signed or $unsigned system-tasks...

Is there a workaround for this ... does ISE 6.3i support it?
(Or does a planned servicepack add $signed/$unsigned support?)