fast adder and equal

And tidy up the sensitivity list ;-)

   counter : process(clk)
   begin
     if rising_edge(clk) then
...
...

Not to mention making cnt an integer type and overflow,
reset, localmode booleans.  This could go on and on so
a wise deity invented comp.lang.vhdl

Symon wrote:
> Rune,
> make everything (more) synchronous. e.g.
>
>   -- clock counter
>   counter : process(clk, cnt, freq_meas)
>   begin
>     if (clk'event and clk = '1') then
>       if (reset = '1') then
>         cnt <= X"000_0000";
>       else
>         cnt <= cnt + 1;
>       end if;
>     -- local mode when reference is missing
>       if (cnt = freq_meas and localmode = '1') then
>         overflow <= '1';
>       else
>         overflow <= '0';
>       end if;
>       reset <= ref_edge or overflow;
>     end if;
>   end process counter;

Whoops, forgot sensitivity list. Because I'm posting in CAF not CLV I should
be cut some slack on my coding! ;-)
IMHO, I think this does belong in this newsgroup; the thread is more about
coding for an FPGA than VHDL per se.
Cheers, Syms.
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message
news:cjcnbh$jut$1$830fa17d@news.demon.co.uk...
> And tidy up the sensitivity list ;-)
>
>    counter : process(clk)
>    begin
>      if rising_edge(clk) then
> ...
> ...
>
> Not to mention making cnt an integer type and overflow,
> reset, localmode booleans.  This could go on and on so
> a wise deity invented comp.lang.vhdl
>