Hi And where can I find the download link for the Verilog model? Because I can nowhere on the project site of aeMB! cheers Roman "Antti Lukats" <antti@case2000.com> wrote in message news:cjbrus$csk$02$1@news.t-online.com...> Hi All > > finally today the project maintainer at opencores uploaded the verilog > design files for MicroBlaze compliant IP-Core. Download is available at > opencores.com - as project aeMB !! > > for PicoBlaze there are 2 different open source 3rd party implementations > known, i wonder when first NIOS-II open source IP-core will be available > :) > > > Antti > xilinx.openchip.org > > > >
Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
Started by ●September 28, 2004
Reply by ●September 28, 20042004-09-28
"Antti Lukats" <antti@case2000.com> wrote in message news:<cjc3ae$ves$01$1@news.t-online.com>...> "Roman Zeilinger" <Patrick.Bateman23@gmx.at> wrote in message > news:2rtd9aF1eq2mjU1@uni-berlin.de... > > Hi > > > > And where can I find the download link for the Verilog model? > > Because I can nowhere on the project site of aeMB! > > > > cheers > > Roman > > http://www.opencores.com/pdownloads.cgi/list/aemb > > get the archive, the verilog source is inside there, checked :) > > AnttiIf you check out the syn directory in that archive it lists the sythesis results for various FPGA's. What is interesting is the frequency of operation in a Xilinx device is >3X the Altera device. I would be very interested to see the results of a Nios-II core in a Xilinx Device!!
Reply by ●September 28, 20042004-09-28
Hi All finally today the project maintainer at opencores uploaded the verilog design files for MicroBlaze compliant IP-Core. Download is available at opencores.com - as project aeMB !! for PicoBlaze there are 2 different open source 3rd party implementations known, i wonder when first NIOS-II open source IP-core will be available :) Antti xilinx.openchip.org
Reply by ●September 28, 20042004-09-28
"Roman Zeilinger" <Patrick.Bateman23@gmx.at> wrote in message news:2rtd9aF1eq2mjU1@uni-berlin.de...> Hi > > And where can I find the download link for the Verilog model? > Because I can nowhere on the project site of aeMB! > > cheers > Romanhttp://www.opencores.com/pdownloads.cgi/list/aemb get the archive, the verilog source is inside there, checked :) Antti
Reply by ●September 29, 20042004-09-29
"Antti Lukats" <antti@case2000.com> wrote in message news:<cjbrus$csk$02$1@news.t-online.com>...> Hi All > > finally today the project maintainer at opencores uploaded the verilog > design files for MicroBlaze compliant IP-Core. Download is available at > opencores.com - as project aeMB !!How long before Xilinx try to get them to remove it do we reckon? Cheers, Jon
Reply by ●September 29, 20042004-09-29
Jon Beniston wrote:> How long before Xilinx try to get them to remove it do we reckon?Why do you think, they should ?
Reply by ●September 29, 20042004-09-29
Tails wrote:> > "Antti Lukats" <antti@case2000.com> wrote in message news:<cjc3ae$ves$01$1@news.t-online.com>... > > "Roman Zeilinger" <Patrick.Bateman23@gmx.at> wrote in message > > news:2rtd9aF1eq2mjU1@uni-berlin.de... > > > Hi > > > > > > And where can I find the download link for the Verilog model? > > > Because I can nowhere on the project site of aeMB! > > > > > > cheers > > > Roman > > > > http://www.opencores.com/pdownloads.cgi/list/aemb > > > > get the archive, the verilog source is inside there, checked :) > > > > Antti > > If you check out the syn directory in that archive it lists the > sythesis results for various FPGA's. What is interesting is the > frequency of operation in a Xilinx device is >3X the Altera device. > > I would be very interested to see the results of a Nios-II core in a > Xilinx Device!!That doesn't suprise me at all. Each vendor has designed their CPU from the ground up knowing exactly how to optimize the design for their architecture. I am sure every little nit was used to optimize the design for speed and size. I expect the xxxxBlaze designs use a lot more LUTs in the Altera parts too! As you say, it will be interesting to see how the Nios-II core fits into a Spartan-3. I will also be interested in seeing how it fits an Altera ACEX which Altera is not supporting with this design. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●September 29, 20042004-09-29
tails_naf@yahoo.com (Tails) writes:> "Antti Lukats" <antti@case2000.com> wrote in message news:<cjc3ae$ves$01$1@news.t-online.com>... > > "Roman Zeilinger" <Patrick.Bateman23@gmx.at> wrote in message > > http://www.opencores.com/pdownloads.cgi/list/aemb > If you check out the syn directory in that archive it lists the > sythesis results for various FPGA's. What is interesting is the > frequency of operation in a Xilinx device is >3X the Altera device.If you look closer you'll see that the Altera devices used are pretty old... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
Reply by ●September 29, 20042004-09-29
In case people start targeting MicroBlaze and its tools at vendor A's parts? ;-) Maybe not! Syms. "E.S." <emu@ecubics.com> wrote in message news:FaA6d.56$hO4.19@fe39.usenetserver.com...> Jon Beniston wrote: > > > How long before Xilinx try to get them to remove it do we reckon? > > Why do you think, they should ? > >
Reply by ●September 29, 20042004-09-29
> > If you check out the syn directory in that archive it lists the > > sythesis results for various FPGA's. What is interesting is the > > frequency of operation in a Xilinx device is >3X the Altera device. > > If you look closer you'll see that the Altera devices used are pretty > old...Very old. In this case, the best Altera part used is an EP20K100TC144-3 -- an original APEX 20K part, in the slowest speed grade. That product was manufactured at 0.25u technology. It is being compared to a XC2V80CS144-6, which IIRC is a 0.15u/0.13u hybrid, and is the fastest available Virtex-II speed grade to boot. QUICK REMINDER: Altera numbers speed grades such that lower = faster. Xilinx numbers things so higher = faster. Also, I should point out that the reported speeds appear to be based on synthesis estimates -- you really need to run place & route before you can ever compare results between two architectures. Synthesis performance estimates give you a reasonable idea of how changes in a given design affect its performance, and they *should* be tuned to give the right answer on average over a large set of designs. But on any given design there's no guarantee the estimate will be close to the final P&R value, and there are both systematic design-specific and completely random components to this error. In short, comparing post-synthesis Fmax across two chips on one design is quite inaccurate. As other users have pointed out, this core may also be optimized towards Xilinx like architectures. I have not looked at it and thus do not know if this is the case. Regards, Paul Leventis Altera Corp.
