Xilinx Read First Write First

What's this Read First or Write First on Xilinx BRAM about?

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10lj8q5o44cr9f2@corp.supernews.com...
> What's this Read First or Write First on Xilinx BRAM about?


If you write to mem[addr] the same clock edge that you read mem[addr] on
that same port, what do you want for the result?

Do you want the old data before the write as if it were a register (read
first) or the brand new data that's in process of being written to the
memory array (write first)?  The Xilinx Software Manuals (library guide)
have the tables that try to explain the nuances.

So, I'm reading and writing on the same clock.  I suppose if I wanted to do
this, maybe for speed, I would want the read to be the old data before the
write. Can't think of any reason I would want the new data going in. I
already have it.

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10ljabn8ca1e8f6@corp.supernews.com...
> So, I'm reading and writing on the same clock.  I suppose if I wanted to
do
> this, maybe for speed, I would want the read to be the old data before the
> write. Can't think of any reason I would want the new data going in. I
> already have it.

A fall-through FIFO is one example where the data going in might be needed
on the output.
If the memory is for storage of values, why not use the most recent value
with a write-first?

Fixed delay-lines are easy to implement with a single address with read
first.

What about a FIFO? If it's empty, you want the first data in to appear right
away.
Cheers, Syms.
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10ljabn8ca1e8f6@corp.supernews.com...
> So, I'm reading and writing on the same clock.  I suppose if I wanted to
do
> this, maybe for speed, I would want the read to be the old data before the
> write. Can't think of any reason I would want the new data going in. I
> already have it.
>
>

Any Virtex BlockRAM always performs a "free" read operation whenever you do
a write.
The data appearing at the data output is either the data previously stored
at that location (and about to be oberwritten), or it is the data you are
just writing, or the data output does not change, keeps holding its old
value. You pick one of these three choices by configuration.

The Virtex-4 FIFO has an optional "fall-through" mode, where data written
into an empty FIFO immediately appears on the read output port.
Responding to a different thread: The Virtex-4 FIFO generate FULL and EMPTY
flags and ALMOST FULL and ALMOST EMPTY flags, all internally synchronized
(rising and falling edges) to the relevant clock domain. We just finished
testing asynchronous operation at 500 MHz read clock rate, with no error in
>10e14 "going empty" cycles.
Peter Alfke, Xilinx Applications

> From: "Symon" <symon_brewer@hotmail.com>
> Newsgroups: comp.arch.fpga
> Date: Tue, 28 Sep 2004 11:28:05 -0700
> Subject: Re: Xilinx Read First Write First
> 
> What about a FIFO? If it's empty, you want the first data in to appear right
> away.
> Cheers, Syms.
> "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
> news:10ljabn8ca1e8f6@corp.supernews.com...
>> So, I'm reading and writing on the same clock.  I suppose if I wanted to
> do
>> this, maybe for speed, I would want the read to be the old data before the
>> write. Can't think of any reason I would want the new data going in. I
>> already have it.
>> 
>> 
> 
> 

It's mainly for compatibility with the behavior of the first BlockRAMs.
Nobody suggests that you should use it in newer designs...
Peter Alfke

> From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
> Organization: Posted via Supernews, http://www.supernews.com
> Newsgroups: comp.arch.fpga
> Date: Tue, 28 Sep 2004 11:11:48 -0700
> Subject: Re: Xilinx Read First Write First
> 
> So, I'm reading and writing on the same clock.  I suppose if I wanted to do
> this, maybe for speed, I would want the read to be the old data before the
> write. Can't think of any reason I would want the new data going in. I
> already have it.
> 
>It's for  

Got it. Thanks.

>The Virtex-4 FIFO has an optional "fall-through" mode, where data written
>into an empty FIFO immediately appears on the read output port.
>Responding to a different thread: The Virtex-4 FIFO generate FULL and EMPTY
>flags and ALMOST FULL and ALMOST EMPTY flags, all internally synchronized
>(rising and falling edges) to the relevant clock domain. We just finished
>testing asynchronous operation at 500 MHz read clock rate, with no error in
>>10e14 "going empty" cycles.
>Peter Alfke, Xilinx Applications

Neat.  Thanks.

Can you measure the metastability parameters?

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How about dual port BRAM? My understanding is that both the ports have
access to the same BRAM. So if in through one port you want to read the
data and through the other port you want to write the data  to same
memory location what will happen?


Thanks