VHDL Project Verilog open core compatibility?

I am interested in the compatibility of a VHDL project instantiating a
verilog open core, floating point arthmetic block. Is this possible
and if it is not is there another way to use a verilog open core
inside a VHDL project, a transform of some kind?

Followup to:  <48eaa469.0409291100.3ae7062a@posting.google.com>
By author:    cyd@spectrum.montana.edu (Cy Drollinger)
In newsgroup: comp.arch.fpga
>
> I am interested in the compatibility of a VHDL project instantiating a
> verilog open core, floating point arthmetic block. Is this possible
> and if it is not is there another way to use a verilog open core
> inside a VHDL project, a transform of some kind?
> 

It depends on your software.  Both Xilinx ISE and Altera Quartus
support it just fine, but if you're using other tools it's up to each
tool.

	-hpa