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RISC-V Support in FPGA

Started by rickman April 28, 2017
I don't recall where, but there was a conversation recently about using 
the RISC-V in FPGAs.  Thought I'd pass on the link.

https://www.microsemi.com/products/fpga-soc/technology-solutions/embedded-processing/risc-v

-- 

Rick C
On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote:

> I don't recall where, but there was a conversation recently about using > the RISC-V in FPGAs. Thought I'd pass on the link. > > https://www.microsemi.com/products/fpga-soc/technology-solutions/
embedded-processing/risc-v Ooh, cool. I'm going to have to keep my eye on the RISC-V. -- Tim Wescott Control systems, embedded software and circuit design I'm looking for work! See my website if you're interested http://www.wescottdesign.com
On 4/28/2017 9:56 PM, Tim Wescott wrote:
> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: > >> I don't recall where, but there was a conversation recently about using >> the RISC-V in FPGAs. Thought I'd pass on the link. >> >> https://www.microsemi.com/products/fpga-soc/technology-solutions/ > embedded-processing/risc-v > > Ooh, cool. I'm going to have to keep my eye on the RISC-V.
I don't know how small the RISC-V can be made. I know there is a version designed in an ASIC that can compete with the ARM CPUs and there are more than one version for FPGAs. I would hope they had a version similar to the ARM CM-1 which is specifically targeted to programmable logic and not overly large. I haven't seen any indication this exists, but it is hard to find this type of info. Or I'm just not looking in the right places. -- Rick C
On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote:

> On 4/28/2017 9:56 PM, Tim Wescott wrote: >> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >> >>> I don't recall where, but there was a conversation recently about >>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>> >>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >> embedded-processing/risc-v >> >> Ooh, cool. I'm going to have to keep my eye on the RISC-V. > > I don't know how small the RISC-V can be made. I know there is a > version designed in an ASIC that can compete with the ARM CPUs and there > are more than one version for FPGAs. I would hope they had a version > similar to the ARM CM-1 which is specifically targeted to programmable > logic and not overly large. I haven't seen any indication this exists, > but it is hard to find this type of info. Or I'm just not looking in > the right places.
They claim to have a minimal variant of the instruction set, which would presumably be an FPGA-ish sort of thing. But I only read about 20 pages into the instruction set document. It's OPEN SOURCE! You could get cracking and make one!! (Well, so could I, theoretically, if I were insane). -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote:

> On 4/28/2017 9:56 PM, Tim Wescott wrote: >> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >> >>> I don't recall where, but there was a conversation recently about >>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>> >>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >> embedded-processing/risc-v >> >> Ooh, cool. I'm going to have to keep my eye on the RISC-V. > > I don't know how small the RISC-V can be made. I know there is a > version designed in an ASIC that can compete with the ARM CPUs and there > are more than one version for FPGAs. I would hope they had a version > similar to the ARM CM-1 which is specifically targeted to programmable > logic and not overly large. I haven't seen any indication this exists, > but it is hard to find this type of info. Or I'm just not looking in > the right places.
Googling RISC-V FPGA implementation got lots of hits. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
On 4/30/2017 12:38 AM, Tim Wescott wrote:
> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: > >> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>> >>>> I don't recall where, but there was a conversation recently about >>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>> >>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>> embedded-processing/risc-v >>> >>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >> >> I don't know how small the RISC-V can be made. I know there is a >> version designed in an ASIC that can compete with the ARM CPUs and there >> are more than one version for FPGAs. I would hope they had a version >> similar to the ARM CM-1 which is specifically targeted to programmable >> logic and not overly large. I haven't seen any indication this exists, >> but it is hard to find this type of info. Or I'm just not looking in >> the right places. > > Googling RISC-V FPGA implementation got lots of hits.
Too many, with all that I checked having little value. I've never understood why people go to all the trouble of designing modules and making them publicly available without significant documentation that explains what was done and why. In some 10 or 12 links I was not able to find a single overview of what the project is about, where it is currently and where it is headed. Whatever. I don't have a strong interest in it at the moment. I have some ideas of my own I want to pursue which is also back burner. -- Rick C
On 4/30/2017 12:35 AM, Tim Wescott wrote:
> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: > >> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>> >>>> I don't recall where, but there was a conversation recently about >>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>> >>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>> embedded-processing/risc-v >>> >>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >> >> I don't know how small the RISC-V can be made. I know there is a >> version designed in an ASIC that can compete with the ARM CPUs and there >> are more than one version for FPGAs. I would hope they had a version >> similar to the ARM CM-1 which is specifically targeted to programmable >> logic and not overly large. I haven't seen any indication this exists, >> but it is hard to find this type of info. Or I'm just not looking in >> the right places. > > They claim to have a minimal variant of the instruction set, which would > presumably be an FPGA-ish sort of thing. But I only read about 20 pages > into the instruction set document.
I found reference to there being as many as three variants implemented in FPGAs, but I don't think any are intended for use in FPGAs. Rather I believe these are just test designs along the road to the ASIC which would seem to be out and available on a board for not too much money.
> It's OPEN SOURCE! You could get cracking and make one!! (Well, so could > I, theoretically, if I were insane).
If I wrote one it would be a very simple implementation which would likely require lots of clock cycles to complete anything. But then maybe my impression of the design is not very accurate. I picture it as something very much more complex than the simple and fast stack processors I am used to working with. -- Rick C
rickman <gnuarm@gmail.com> wrote:
> I don't know how small the RISC-V can be made. I know there is a > version designed in an ASIC that can compete with the ARM CPUs and there > are more than one version for FPGAs. I would hope they had a version > similar to the ARM CM-1 which is specifically targeted to programmable > logic and not overly large. I haven't seen any indication this exists, > but it is hard to find this type of info. Or I'm just not looking in > the right places.
A basic RV32I (the minimal 32 bit user-mode instruction set) is very simple. Here's one that's about 400 lines of SystemVerilog, that was designed by a student over a few weeks as a summer project: https://github.com/ucam-comparch/clarvi Theo
rickman <gnuarm@gmail.com> wrote:
> Too many, with all that I checked having little value. I've never > understood why people go to all the trouble of designing modules and > making them publicly available without significant documentation that > explains what was done and why. In some 10 or 12 links I was not able > to find a single overview of what the project is about, where it is > currently and where it is headed.
https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf is the manifesto. Theo
On Sun, 30 Apr 2017 01:50:42 -0400, rickman wrote:

> On 4/30/2017 12:35 AM, Tim Wescott wrote: >> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >> >>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>> >>>>> I don't recall where, but there was a conversation recently about >>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>> >>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>> embedded-processing/risc-v >>>> >>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>> >>> I don't know how small the RISC-V can be made. I know there is a >>> version designed in an ASIC that can compete with the ARM CPUs and >>> there are more than one version for FPGAs. I would hope they had a >>> version similar to the ARM CM-1 which is specifically targeted to >>> programmable logic and not overly large. I haven't seen any >>> indication this exists, but it is hard to find this type of info. Or >>> I'm just not looking in the right places. >> >> They claim to have a minimal variant of the instruction set, which >> would presumably be an FPGA-ish sort of thing. But I only read about >> 20 pages into the instruction set document. > > I found reference to there being as many as three variants implemented > in FPGAs, but I don't think any are intended for use in FPGAs. Rather I > believe these are just test designs along the road to the ASIC which > would seem to be out and available on a board for not too much money. > > >> It's OPEN SOURCE! You could get cracking and make one!! (Well, so >> could I, theoretically, if I were insane). > > If I wrote one it would be a very simple implementation which would > likely require lots of clock cycles to complete anything. But then > maybe my impression of the design is not very accurate. I picture it as > something very much more complex than the simple and fast stack > processors I am used to working with.
I would at least hope that the result would be on the level of gate usage as a Cortex M1. OTOH, since Day 1, the RISC architecture has been about getting the most bang for your logic buck -- and you can always leave out the bells and whistles like branch prediction and pipelines and whatnot. If they did their job right, you'll find that much of the "logic" can be coded as static wires -- that's why they do things like always have information fields (like register addresses, or immediate data) appearing in the same spots. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!