On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote:> On 4/30/2017 12:38 AM, Tim Wescott wrote: >> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >> >>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>> >>>>> I don't recall where, but there was a conversation recently about >>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>> >>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>> embedded-processing/risc-v >>>> >>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>> >>> I don't know how small the RISC-V can be made. I know there is a >>> version designed in an ASIC that can compete with the ARM CPUs and >>> there are more than one version for FPGAs. I would hope they had a >>> version similar to the ARM CM-1 which is specifically targeted to >>> programmable logic and not overly large. I haven't seen any >>> indication this exists, but it is hard to find this type of info. Or >>> I'm just not looking in the right places. >> >> Googling RISC-V FPGA implementation got lots of hits. > > Too many, with all that I checked having little value. I've never > understood why people go to all the trouble of designing modules and > making them publicly available without significant documentation that > explains what was done and why. In some 10 or 12 links I was not able > to find a single overview of what the project is about, where it is > currently and where it is headed.That's typical of open-source projects: functionality is fun; good documentation is at least as time-consuming as good code (HDL or software), and documentation-writing isn't nearly as fun. For cutting-edge open-source stuff the key to success is to find the web forum or mailing list that covers the subject, and to start asking questions. I suppose that if I won the lottery and didn't get seduced by Tahiti I'd pick a project and just write documentation. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
RISC-V Support in FPGA
Started by ●April 28, 2017
Reply by ●April 30, 20172017-04-30
Reply by ●April 30, 20172017-04-30
On 30/04/17 16:39, Tim Wescott wrote:> On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote: > >> On 4/30/2017 12:38 AM, Tim Wescott wrote: >>> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >>> >>>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>>> >>>>>> I don't recall where, but there was a conversation recently about >>>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>>> >>>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>>> embedded-processing/risc-v >>>>> >>>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>>> >>>> I don't know how small the RISC-V can be made. I know there is a >>>> version designed in an ASIC that can compete with the ARM CPUs and >>>> there are more than one version for FPGAs. I would hope they had a >>>> version similar to the ARM CM-1 which is specifically targeted to >>>> programmable logic and not overly large. I haven't seen any >>>> indication this exists, but it is hard to find this type of info. Or >>>> I'm just not looking in the right places. >>> >>> Googling RISC-V FPGA implementation got lots of hits. >> >> Too many, with all that I checked having little value. I've never >> understood why people go to all the trouble of designing modules and >> making them publicly available without significant documentation that >> explains what was done and why. In some 10 or 12 links I was not able >> to find a single overview of what the project is about, where it is >> currently and where it is headed. > > That's typical of open-source projects: functionality is fun; good > documentation is at least as time-consuming as good code (HDL or > software), and documentation-writing isn't nearly as fun. > > For cutting-edge open-source stuff the key to success is to find the web > forum or mailing list that covers the subject, and to start asking > questions. I suppose that if I won the lottery and didn't get seduced by > Tahiti I'd pick a project and just write documentation. >Or you find a company (ideally run by at least some of the people behind the open source project) that will provide you with support, documentation, demos, point-and-click installations (especially for Windows), etc. - all for a bit of money. When it works well, it can give you all the benefits of a good open source project, /and/ all the benefits of a good commercial project, for a price somewhere in between. I don't know if there is such commercial support available for RISC-V - but if it gets popular enough, then I am sure there will be.
Reply by ●April 30, 20172017-04-30
An older version of the Risc V processor generator is here: https://github.com/ucb-bar/riscv-sodor This is the 1 stage version: https://github.com/ucb-bar/riscv-sodor/tree/master/src/rv32_1stage A more recent version by the same group seems to be this BOOM Risc V which is synthesizable. https://github.com/ucb-bar/riscv-boom This presentation seems to cover all versions: https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf The CPU is implemented in Chisel which is a scala library that compiles to Verilog or C++. https://chisel.eecs.berkeley.edu/2.2.0/getting-started.html On Sunday, April 30, 2017 at 6:13:37 PM UTC+3, David Brown wrote:> On 30/04/17 16:39, Tim Wescott wrote: > > On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote: > > > >> On 4/30/2017 12:38 AM, Tim Wescott wrote: > >>> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: > >>> > >>>> On 4/28/2017 9:56 PM, Tim Wescott wrote: > >>>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: > >>>>> > >>>>>> I don't recall where, but there was a conversation recently about > >>>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. > >>>>>> > >>>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ > >>>>> embedded-processing/risc-v > >>>>> > >>>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. > >>>> > >>>> I don't know how small the RISC-V can be made. I know there is a > >>>> version designed in an ASIC that can compete with the ARM CPUs and > >>>> there are more than one version for FPGAs. I would hope they had a > >>>> version similar to the ARM CM-1 which is specifically targeted to > >>>> programmable logic and not overly large. I haven't seen any > >>>> indication this exists, but it is hard to find this type of info. Or > >>>> I'm just not looking in the right places. > >>> > >>> Googling RISC-V FPGA implementation got lots of hits. > >> > >> Too many, with all that I checked having little value. I've never > >> understood why people go to all the trouble of designing modules and > >> making them publicly available without significant documentation that > >> explains what was done and why. In some 10 or 12 links I was not able > >> to find a single overview of what the project is about, where it is > >> currently and where it is headed. > > > > That's typical of open-source projects: functionality is fun; good > > documentation is at least as time-consuming as good code (HDL or > > software), and documentation-writing isn't nearly as fun. > > > > For cutting-edge open-source stuff the key to success is to find the web > > forum or mailing list that covers the subject, and to start asking > > questions. I suppose that if I won the lottery and didn't get seduced by > > Tahiti I'd pick a project and just write documentation. > > > > Or you find a company (ideally run by at least some of the people behind > the open source project) that will provide you with support, > documentation, demos, point-and-click installations (especially for > Windows), etc. - all for a bit of money. When it works well, it can > give you all the benefits of a good open source project, /and/ all the > benefits of a good commercial project, for a price somewhere in between. > > I don't know if there is such commercial support available for RISC-V - > but if it gets popular enough, then I am sure there will be.
Reply by ●April 30, 20172017-04-30
Tim, all, On 30-04-17 16:39, Tim Wescott wrote: (...)> For cutting-edge open-source stuff the key to success is to find the web > forum or mailing list that covers the subject, and to start asking > questions. I suppose that if I won the lottery and didn't get seduced by > Tahiti I'd pick a project and just write documentation.F.Y.I. One of the main mailing-lists is here: hw-dev@groups.riscv.org Traffic is relative low (about 15 messages a week), so quite easy to follow without getting flooded in messages. more info: https://riscv.org/mailing-lists/ Kristoff
Reply by ●April 30, 20172017-04-30
Emilian Miron <emilian.miron@gmail.com> wrote:> An older version of the Risc V processor generator is here: > https://github.com/ucb-bar/riscv-sodor > This is the 1 stage version: > https://github.com/ucb-bar/riscv-sodor/tree/master/src/rv32_1stage > > A more recent version by the same group seems to be this BOOM Risc V which is synthesizable. > https://github.com/ucb-bar/riscv-boom > > This presentation seems to cover all versions: > https://riscv.org/wp-content/uploads/2016/01/Wed1345-RISCV-Workshop-3-BOOM.pdf > > The CPU is implemented in Chisel which is a scala library that compiles to Verilog or C++. > https://chisel.eecs.berkeley.edu/2.2.0/getting-started.htmlFor those who are confused, RISC-V is not a *processor*, it's an *architecture*. Anyone can come up with a microarchitectural implementation of the architecture - that's the point of an open source ISA. Being open-source you can also change the architecture - but it's then your problem to maintain the OS/compiler/etc for your fork of the architecture. Berkeley happen to have some of their own implementations that they have also open sourced. These might or might not suit your purposes. Being in Chisel is one thing that's not everyone's cup of tea. But the idea is that everyone has an architectural licence, so they are free to come up with their own implementations, and share them. I suspect that Microsemi have done their own, rather than importing the Berkeley cores, for instance. (That RISC-V bears a certain resemblance to MIPS is not entirely accidental; MIPS has long been used as a simple ISA for teaching, which is one role that RISC-V fills without treading on any toes [patents] of Imagination Technologies) Theo
Reply by ●April 30, 20172017-04-30
On 4/30/2017 10:04 AM, Theo Markettos wrote:> rickman <gnuarm@gmail.com> wrote: >> Too many, with all that I checked having little value. I've never >> understood why people go to all the trouble of designing modules and >> making them publicly available without significant documentation that >> explains what was done and why. In some 10 or 12 links I was not able >> to find a single overview of what the project is about, where it is >> currently and where it is headed. > > https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf > is the manifesto.Thanks for the link, this is useful to learn about the instruction set. Not much info on the available implementations. -- Rick C
Reply by ●April 30, 20172017-04-30
On 4/30/2017 10:39 AM, Tim Wescott wrote:> On Sun, 30 Apr 2017 01:46:54 -0400, rickman wrote: > >> On 4/30/2017 12:38 AM, Tim Wescott wrote: >>> On Sat, 29 Apr 2017 23:04:28 -0400, rickman wrote: >>> >>>> On 4/28/2017 9:56 PM, Tim Wescott wrote: >>>>> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >>>>> >>>>>> I don't recall where, but there was a conversation recently about >>>>>> using the RISC-V in FPGAs. Thought I'd pass on the link. >>>>>> >>>>>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >>>>> embedded-processing/risc-v >>>>> >>>>> Ooh, cool. I'm going to have to keep my eye on the RISC-V. >>>> >>>> I don't know how small the RISC-V can be made. I know there is a >>>> version designed in an ASIC that can compete with the ARM CPUs and >>>> there are more than one version for FPGAs. I would hope they had a >>>> version similar to the ARM CM-1 which is specifically targeted to >>>> programmable logic and not overly large. I haven't seen any >>>> indication this exists, but it is hard to find this type of info. Or >>>> I'm just not looking in the right places. >>> >>> Googling RISC-V FPGA implementation got lots of hits. >> >> Too many, with all that I checked having little value. I've never >> understood why people go to all the trouble of designing modules and >> making them publicly available without significant documentation that >> explains what was done and why. In some 10 or 12 links I was not able >> to find a single overview of what the project is about, where it is >> currently and where it is headed. > > That's typical of open-source projects: functionality is fun; good > documentation is at least as time-consuming as good code (HDL or > software), and documentation-writing isn't nearly as fun. > > For cutting-edge open-source stuff the key to success is to find the web > forum or mailing list that covers the subject, and to start asking > questions. I suppose that if I won the lottery and didn't get seduced by > Tahiti I'd pick a project and just write documentation.I see a total lack of documentation on amateur projects where someone designs something and tosses it up on one of the source sharing sites. But a major project like this is about being used. I don't think this is just a few guys who thought it would be cool to design a chip. This chip has been built as an ASIC and has multiple incarnations for FPGA. It would tremendously help encourage implementations to have a decent description of what is available. -- Rick C
Reply by ●May 1, 20172017-05-01
Pretty small (and fast): https://forums.xilinx.com/t5/Xcell-Daily-Blog/1680-open-source-ISA-RISC-V-processor-cores-run-on-one-Virtex/ba-p/742731 On 04/29/2017 08:04 PM, rickman wrote:> On 4/28/2017 9:56 PM, Tim Wescott wrote: >> On Fri, 28 Apr 2017 14:54:06 -0400, rickman wrote: >> >>> I don't recall where, but there was a conversation recently about using >>> the RISC-V in FPGAs. Thought I'd pass on the link. >>> >>> https://www.microsemi.com/products/fpga-soc/technology-solutions/ >> embedded-processing/risc-v >> >> Ooh, cool. I'm going to have to keep my eye on the RISC-V. > > I don't know how small the RISC-V can be made. I know there is a > version designed in an ASIC that can compete with the ARM CPUs and there > are more than one version for FPGAs. I would hope they had a version > similar to the ARM CM-1 which is specifically targeted to programmable > logic and not overly large. I haven't seen any indication this exists, > but it is hard to find this type of info. Or I'm just not looking in > the right places. >
Reply by ●May 1, 20172017-05-01
> That's typical of open-source projects: functionality is fun; good > documentation is at least as time-consuming as good code (HDL or > software), and documentation-writing isn't nearly as fun. > > For cutting-edge open-source stuff the key to success is to find the web > forum or mailing list that covers the subject, and to start asking > questions. I suppose that if I won the lottery and didn't get seduced by > Tahiti I'd pick a project and just write documentation. >I suppose this is one reason that Octave works so well for me: when I have a question, I consult the Matlab documentation. That makes feel a little guilty. I've found Octave is actually faster on a lot of my scripts though. Sadly, when you mentioned Tahiti, I was trying to figure out if that was the name of some obscure HDL or open-source project. It took me a minute to figure out you meant the place where Gaugin hung out. Yeah, that might be better than writing documentation.
Reply by ●May 1, 20172017-05-01
> A basic RV32I (the minimal 32 bit user-mode instruction set) is very simple. > Here's one that's about 400 lines of SystemVerilog, that was designed by a > student over a few weeks as a summer project: > > https://github.com/ucam-comparch/clarvi > > TheoThe code looks pretty clear at first glance. I see a lot of SystemVerilog constructs that don't look synthesizer-friendly, though.
