VHDL or Verilog?

I've been given conflicting device on which language to use.  There
are people I would consider to be expert professionals who tell me
to use VHDL, and others who tell me Verilog.  Most everybody tells
me that if I use VHDL there's less chance for error, but that it
does take more effort to learn.

Any thoughts?

Thank you,
Rick C. Hodgin

Rick C. Hodgin wrote on 6/21/2017 8:08 AM:
> I've been given conflicting device on which language to use.  There
> are people I would consider to be expert professionals who tell me
> to use VHDL, and others who tell me Verilog.  Most everybody tells
> me that if I use VHDL there's less chance for error, but that it
> does take more effort to learn.
>
> Any thoughts?

I don't recommend one over the other.  It's like asking if steak is "better" 
than Sea Bass.  It depends more on the user than the language.

Verilog has a lot in common with C.  It is more brief to type than VHDL, it 
allows some things to be implied through defaults rather than specified 
explicitly and can be much faster to come up to speed with.  VHDL is much 
more verbose, requires *everything* to be indicated explicitly and can be 
hard to get up to speed with a longer learning curve.

When people talk about "less chance for error" they are referring to the 
strong typing and requirement that everything be explicit.  In Verilog you 
can write code that uses the defaults for type conversions and even things 
like word size adjustments.  So if you aren't familiar with all these 
defaults it may not do what you were hoping for.  In VHDL you don't get to 
take the shortcuts and *must* convert types and adjust all operands and 
results to match.  Otherwise you get error messages that don't always tell 
you what you did wrong.

Personally I find VHDL to be ok, but that is mostly because I've used it for 
some 20 years.  The only thing holding me back from working in Verilog is no 
one can recommend a good Verilog book that covers all the pitfalls.  I've 
been told many times that a good Verilog book has yet to be written.

If you want to learn both (what I actually recommend) I suggest you learn 
VHDL first, get good enough at it that you don't swear every time you have 
to type convert an integer, and only *then* learn Verilog.  Then you will 
have given VHDL a decent chance and you can make your own decision whether 
Verilog is your preference.  I'm pretty sure once you learn Verilog you will 
find learning VHDL to be very annoying.

-- 

Rick C

On Wednesday, June 21, 2017 at 11:20:04 AM UTC-4, rickman wrote:
> Rick C. Hodgin wrote on 6/21/2017 8:08 AM:
> > I've been given conflicting device on which language to use.  There
> > are people I would consider to be expert professionals who tell me
> > to use VHDL, and others who tell me Verilog.  Most everybody tells
> > me that if I use VHDL there's less chance for error, but that it
> > does take more effort to learn.
> >
> > Any thoughts?
> 
> I don't recommend one over the other.  It's like asking if steak is "better" 
> than Sea Bass.  It depends more on the user than the language.
> 
> Verilog has a lot in common with C.  It is more brief to type than VHDL, it 
> allows some things to be implied through defaults rather than specified 
> explicitly and can be much faster to come up to speed with.  VHDL is much 
> more verbose, requires *everything* to be indicated explicitly and can be 
> hard to get up to speed with a longer learning curve.
> 
> When people talk about "less chance for error" they are referring to the 
> strong typing and requirement that everything be explicit.  In Verilog you 
> can write code that uses the defaults for type conversions and even things 
> like word size adjustments.  So if you aren't familiar with all these 
> defaults it may not do what you were hoping for.  In VHDL you don't get to 
> take the shortcuts and *must* convert types and adjust all operands and 
> results to match.  Otherwise you get error messages that don't always tell 
> you what you did wrong.
> 
> Personally I find VHDL to be ok, but that is mostly because I've used it for 
> some 20 years.  The only thing holding me back from working in Verilog is no 
> one can recommend a good Verilog book that covers all the pitfalls.  I've 
> been told many times that a good Verilog book has yet to be written.
> 
> If you want to learn both (what I actually recommend) I suggest you learn 
> VHDL first, get good enough at it that you don't swear every time you have 
> to type convert an integer, and only *then* learn Verilog.  Then you will 
> have given VHDL a decent chance and you can make your own decision whether 
> Verilog is your preference.  I'm pretty sure once you learn Verilog you will 
> find learning VHDL to be very annoying.

I've had difficulty with the mechanics of Verilog.  I have been able
to go through examples on EDA Playground, for example, but there are
a handful of things I don't yet understand, and they are hindering
me from being able to express ideas into this hardware source code.

I have contacted a local group here in Indianapolis, IN, and they
have some members with hardware skills.  I think they'll be able
to help me.  One of the members there suggested VHDL well ahead of
Verilog.  But for now, I'm going to switch to Arduino and at least
get my prototypes working, even if they're limited, while I spend
my evenings and weekends trying to get the same logic encoded in
my FPGA.

I appreciate your response.  Thank you, Rick C.

Thank you,
Rick C. Hodgin

> Any thoughts?

My thought is that you should start with vhdl and ghdl for simulation and g=
tkwave for viewing. Or just use Vivado web edition if you want to do things=
 in a gui. It is not that much of a learning curve with all the example cod=
e available on the net. Most of the tricky things with vhdl and types has a=
lready been asked at least once, so google will find solutions to just abou=
t any problem you may have in the beginning. It is always possible to go to=
 verilog later if you find that vhdl is not for you. With the good mixed la=
nguage support in vivado, you would not waste much of your time learning ei=
ther. But I never cared to move to verilog so what do I know. (I do transla=
te verilog code to vhdl with icarus or by hand so it is not that I haven't =
been exposed to verilog)

--=20
Svenn

On 21/06/17 17:20, rickman wrote:
> Rick C. Hodgin wrote on 6/21/2017 8:08 AM:
>> I've been given conflicting device on which language to use.  There
>> are people I would consider to be expert professionals who tell me
>> to use VHDL, and others who tell me Verilog.  Most everybody tells
>> me that if I use VHDL there's less chance for error, but that it
>> does take more effort to learn.
>>
>> Any thoughts?
> 
> I don't recommend one over the other.  It's like asking if steak is 
> "better" than Sea Bass.  It depends more on the user than the language.
> 
> Verilog has a lot in common with C.  It is more brief to type than VHDL, 
> it allows some things to be implied through defaults rather than 
> specified explicitly and can be much faster to come up to speed with.  
> VHDL is much more verbose, requires *everything* to be indicated 
> explicitly and can be hard to get up to speed with a longer learning curve.
> 
> When people talk about "less chance for error" they are referring to the 
> strong typing and requirement that everything be explicit.  In Verilog 
> you can write code that uses the defaults for type conversions and even 
> things like word size adjustments.  So if you aren't familiar with all 
> these defaults it may not do what you were hoping for.  In VHDL you 
> don't get to take the shortcuts and *must* convert types and adjust all 
> operands and results to match.  Otherwise you get error messages that 
> don't always tell you what you did wrong.
> 
> Personally I find VHDL to be ok, but that is mostly because I've used it 
> for some 20 years.  The only thing holding me back from working in 
> Verilog is no one can recommend a good Verilog book that covers all the 
> pitfalls.  I've been told many times that a good Verilog book has yet to 
> be written.
> 
> If you want to learn both (what I actually recommend) I suggest you 
> learn VHDL first, get good enough at it that you don't swear every time 
> you have to type convert an integer, and only *then* learn Verilog.  
> Then you will have given VHDL a decent chance and you can make your own 
> decision whether Verilog is your preference.  I'm pretty sure once you 
> learn Verilog you will find learning VHDL to be very annoying.
> 

Have you any experience with hardware design languages other than "the 
big two" ?  There are many other possibilities, such as SystemC, 
SystemVerilog, MyHDL, Lava, etc.  I used Confluence for a couple of 
designs, many years ago - it is a functional programming HDL language. 
I found it good for making flexible designs with clean synchronous 
logic, using a fraction of the code needed in Verilog or VHDL for the 
same job.

Den onsdag den 21. juni 2017 kl. 14.08.53 UTC+2 skrev Rick C. Hodgin:
> I've been given conflicting device on which language to use.  There
> are people I would consider to be expert professionals who tell me
> to use VHDL, and others who tell me Verilog.  Most everybody tells
> me that if I use VHDL there's less chance for error, but that it
> does take more effort to learn.
> 
> Any thoughts?
> 

don't you already have enough arguments over religion? ;)

lasselangwadtchristensen@gmail.com wrote on 6/21/2017 5:05 PM:
> Den onsdag den 21. juni 2017 kl. 14.08.53 UTC+2 skrev Rick C. Hodgin:
>> I've been given conflicting device on which language to use.  There
>> are people I would consider to be expert professionals who tell me
>> to use VHDL, and others who tell me Verilog.  Most everybody tells
>> me that if I use VHDL there's less chance for error, but that it
>> does take more effort to learn.
>>
>> Any thoughts?
>>
>
> don't you already have enough arguments over religion? ;)

I feel that is uncalled for.  When he comes here proselytizing then respond 
about that (or better ignore him).  But when he comes here like the rest of 
us asking for technical help, why pick on him?

-- 

Rick C

On Wednesday, June 21, 2017 at 5:05:50 PM UTC-4, lasselangwad...@gmail.com wrote:
> Den onsdag den 21. juni 2017 kl. 14.08.53 UTC+2 skrev Rick C. Hodgin:
> > I've been given conflicting device on which language to use.  There
> > are people I would consider to be expert professionals who tell me
> > to use VHDL, and others who tell me Verilog.  Most everybody tells
> > me that if I use VHDL there's less chance for error, but that it
> > does take more effort to learn.
> > 
> > Any thoughts?
> 
> don't you already have enough arguments over religion? ;)

LOL!  I didn't know.  I plea ignorance.

Thank you,
Rick C. Hodgin

On Wednesday, June 21, 2017 at 5:17:24 PM UTC-4, rickman wrote:
> lasselangwadtchristensen@gmail.com wrote on 6/21/2017 5:05 PM:
> > Den onsdag den 21. juni 2017 kl. 14.08.53 UTC+2 skrev Rick C. Hodgin:
> >> I've been given conflicting device on which language to use.  There
> >> are people I would consider to be expert professionals who tell me
> >> to use VHDL, and others who tell me Verilog.  Most everybody tells
> >> me that if I use VHDL there's less chance for error, but that it
> >> does take more effort to learn.
> >>
> >> Any thoughts?
> >>
> >
> > don't you already have enough arguments over religion? ;)
> 
> I feel that is uncalled for.  When he comes here proselytizing then respond 
> about that (or better ignore him).  But when he comes here like the rest of 
> us asking for technical help, why pick on him?

It's okay.  I thought it was very funny actually.  I couldn't
respond more timely though because I was at a stop light when
I read it. :-)

Thank you,
Rick C. Hodgin

Rick C. Hodgin wrote on 6/21/2017 5:28 PM:
> On Wednesday, June 21, 2017 at 5:17:24 PM UTC-4, rickman wrote:
>> lasselangwadtchristensen@gmail.com wrote on 6/21/2017 5:05 PM:
>>> Den onsdag den 21. juni 2017 kl. 14.08.53 UTC+2 skrev Rick C. Hodgin:
>>>> I've been given conflicting device on which language to use.  There
>>>> are people I would consider to be expert professionals who tell me
>>>> to use VHDL, and others who tell me Verilog.  Most everybody tells
>>>> me that if I use VHDL there's less chance for error, but that it
>>>> does take more effort to learn.
>>>>
>>>> Any thoughts?
>>>>
>>>
>>> don't you already have enough arguments over religion? ;)
>>
>> I feel that is uncalled for.  When he comes here proselytizing then respond
>> about that (or better ignore him).  But when he comes here like the rest of
>> us asking for technical help, why pick on him?
>
> It's okay.  I thought it was very funny actually.  I couldn't
> respond more timely though because I was at a stop light when
> I read it. :-)

Actually I guess it was rather a joke instead of an insult.  I didn't pick 
up on that.  VHDL vs. Verilog can very much be a religious war.

Sorry Lasse.

-- 

Rick C