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minimal HDMI pins to send video ?

Started by Unknown August 3, 2017
Dear all 

who knows 4 pairs of 

1)  CLOCK+, CLOCK-
2)  TMDS2+, TMDS2-
3)  TMDS1+, TMDS1-
4)  TMDS0+, TMDS0-

are enough to send video by HDMI or need to generate some other signals ?
 
 1)  CLOCK+, CLOCK-
 2)  TMDS2+, TMDS2-
 3)  TMDS1+, TMDS1-
 4)  TMDS0+, TMDS0-
 
 5) GND connected to pins (2,5,8,11,17,pins or connector housing)

and ground connected to 2,5,8,11,17 pins and housing.
On Thursday, August 3, 2017 at 7:49:53 AM UTC-3, abi...@gmail.com wrote:
> Dear all > > who knows 4 pairs of > > 1) CLOCK+, CLOCK- > 2) TMDS2+, TMDS2- > 3) TMDS1+, TMDS1- > 4) TMDS0+, TMDS0- > > are enough to send video by HDMI or need to generate some other signals ?
I thought an I2C interface would also be needed, but it seems not: http://www.fpga4fun.com/HDMI.html -- Jecel
On Thursday, August 3, 2017 at 7:49:53 AM UTC-3, abi...@gmail.com wrote:
> Dear all > > who knows 4 pairs of > > 1) CLOCK+, CLOCK- > 2) TMDS2+, TMDS2- > 3) TMDS1+, TMDS1- > 4) TMDS0+, TMDS0- > > are enough to send video by HDMI or need to generate some other signals ?
http://www.fpga4fun.com/HDMI.html shows examples with just those 8 FPGA pins
On 8/3/17 12:50 PM, Jecel wrote:
> On Thursday, August 3, 2017 at 7:49:53 AM UTC-3, abi...@gmail.com wrote: >> Dear all >> >> who knows 4 pairs of >> >> 1) CLOCK+, CLOCK- >> 2) TMDS2+, TMDS2- >> 3) TMDS1+, TMDS1- >> 4) TMDS0+, TMDS0- >> >> are enough to send video by HDMI or need to generate some other signals ? > > I thought an I2C interface would also be needed, but it seems not: > > http://www.fpga4fun.com/HDMI.html > > -- Jecel >
The I2C bus is to provide capability information about the display to the controller (it is often just a simple I2C rom). If the transmitter already knows how it is going to send (or is configured by the user) it doesn't need to send anything on the I2C bus.
I am VHDL user , how to declare correctly : 

i thought pixclk must be declare like this  :

reg pixclk;

clock instance_name (
    .CLKIN_IN(clk100), 
    .CLKDV_OUT(pixclk), 
    .CLKFX_OUT(DCM_TMDS_CLKFX), 
    .CLKIN_IBUFG_OUT(clk_TMDS), 
    .CLK0_OUT(CLK0_OUT)
    );

ERROR:HDLCompilers:246 - "asdf.v" line 48 Reference to scalar reg 'pixclk' is not a legal net lvalue
ERROR:HDLCompilers:102 - "asdf.v" line 48 Connection to output port 'CLKDV_OUT' must be a net lvalue
On Friday, 8/4/2017 5:33 AM, abirov@gmail.com wrote:
> I am VHDL user , how to declare correctly : > > i thought pixclk must be declare like this : > > reg pixclk; > > clock instance_name ( > .CLKIN_IN(clk100), > .CLKDV_OUT(pixclk), > .CLKFX_OUT(DCM_TMDS_CLKFX), > .CLKIN_IBUFG_OUT(clk_TMDS), > .CLK0_OUT(CLK0_OUT) > ); > > ERROR:HDLCompilers:246 - "asdf.v" line 48 Reference to scalar reg 'pixclk' is not a legal net lvalue > ERROR:HDLCompilers:102 - "asdf.v" line 48 Connection to output port 'CLKDV_OUT' must be a net lvalue >
reg pixclk; should be: wire pixclk; Compiler errors are a bit obtuse, but the idea is that a reg is different from a wire in that it is meant to be assigned in a process only. A wire may only be assigned outside a process, in a continuous assignment or port connection as in your code. In SystemVerilog, you can declare a signal as "logic" and then use it anywhere you like. The above is simplified greatly. I'd recommend a good book on Verilog, but the only ones I'm familiar with are pretty much outdated. -- Gabor