SystemVerilog and alternatives

Started by tullio August 8, 2017
Hello,

 i am an experienced FPGA designer, having used Verilog for long time.
For a mixed analog-digital project involving an ASIC and (maybe) an FPGA, i need to
get ready for extensive verification and test-vector generation.
The mainstream tools seem to be SystemVerilog and UVM, which seem to have a
difficult learning curve and also difficult maintenance.
But somebody suggested me to consider using Verilog and Python, having the advantage
that they complement each other very nicely, and that Python is easy to learn.

Can anybody share experiences from real projects ?

Thanks,
  Tullio

I have used cocotb to verify some modules recently. Fairly straightforward to get
going and to write stimulators and checkers. There are some things I didn't like (eg
it deletes the work library and recompiles on every run) but it it uses make files
to set up and run the sim so I found it easy to hack it to make it behave how I
wanted. 

I like to use python for algorithm development and modelling so it could not be
easier to reuse the model code in the python test bench. 

My modules were in vhdl but it works with verilog.
On Tue, 8 Aug 2017 04:00:59 -0700 (PDT)
tullio <tullio.grassi@gmail.com> wrote:

> Hello, > > i am an experienced FPGA designer, having used Verilog for > long time. For a mixed analog-digital project involving an > ASIC and (maybe) an FPGA, i need to get ready for extensive > verification and test-vector generation. The mainstream tools > seem to be SystemVerilog and UVM, which seem to have a > difficult learning curve and also difficult maintenance. But > somebody suggested me to consider using Verilog and Python, > having the advantage that they complement each other very > nicely, and that Python is easy to learn.
Could that last point be simplified by building your simulation model and tests in python using the MyHDL library? From this you can then export Verilog or VHDL for synthesis. Jan Coombs -- http://myhdl.org/