for the case of registers dependencies, d <= c <= b <= a , how do we assert d whenever a is asserted without cheating the delay ?
Started by ●August 30, 2017
Posted by ●August 30, 2017
This is kind of vague and depends what you want to do with it and why, but you can always do something like: d <= c | a; If "a" is only asserted for one clock cycle, then you would get two pulses on "d." Are you trying to do that, or are you trying to extend "a" to a longer pulse? On Wednesday, August 30, 2017 at 9:20:46 AM UTC-7, promach wrote:> for the case of registers dependencies, d <= c <= b <= a , how do we assert dwhenever a is asserted without cheating the delay ?