Request for an example in Verilog

Dear All,

I am a student with primitive experience in verilog. I have a small verific=
ation task for a top module. I have simplified the task in the below descri=
ption, so that you can give me a quick response. There could be solve for t=
his problem in various ways. But ideally I am finding a solution to create =
an automatic test setup.

Please find below the problem. If you could write me a solution with a work=
ing example in verilog, that would be a good starting point.

Write a Script or Test bench for the following tasks;
Send Data =3D 8 bits and Received Data is 16 bits.

1. First Send Data for 0-256 data frames with STATUS_IN =3D 0, and then aga=
in Send Data 0-256 data frames with STATUS_IN =3D 1
2. Next send few control frames of 8 bits with specific pattern (e.g. 8'b00=
110101) again with STATUS_IN =3D 0 and STATUS_IN =3D 1
3. Compare if Send Data =3D=3D Received Data at the DATA_OUT port. Also com=
pare if STATUS_IN =3D=3D STATUS_OUT for every received data frame
4. Print SUCCESS or FAIL for every data frame transmission in a File (use F=
ile handling)
File handling: Print Send Data and Received Data, Print STATUS_IN and STATU=
S_OUT and SUCCESS and FAIL for each data frame transmission

One additional task is to breaking 16 bits Received Data in two 8 bits for =
each cycle. Find attached the diagram of the module.