ModelSim

Where are there some really easy point and click tutorials for ModelSIM?

modelsim isn't really that difficult to use... its the VHDL or verilog
testbench that's the bugger.

Simon

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10n10gn1546dba4@corp.supernews.com...
> Where are there some really easy point and click tutorials for ModelSIM?
>
>

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message 
news:10n10gn1546dba4@corp.supernews.com...
> Where are there some really easy point and click tutorials for ModelSIM?

It comes with quite a good introductory tutorial.

Leon 

Yeah. I am gathering that. And it is also difficult to understand where VHDL
testbenches  "begins" and the other takes over. There is also a waveformer
in the Xilinx tool that is somewhat intuitive. I have found some text books
that cover simulation testbenches and give a few examples. Very week though
in terms of the numbers of examples and the strategy behind the use of the
various commands. I still haven't found an example of a bidirectional test
bench.  I also started searching the web with the words downto and testbench
and have found some examples, but these are not what I would call good
tutorials.

"Simon Peacock" <nowhere@to.be.found> wrote in message
news:4171044a@news.actrix.gen.nz...
> modelsim isn't really that difficult to use... its the VHDL or verilog
> testbench that's the bugger.
>
> Simon
>

> It comes with quite a good introductory tutorial.

The 58 page one?

Brad Smallridge wrote:
> Yeah. I am gathering that. And it is also difficult to understand where VHDL
> testbenches  "begins" and the other takes over. 

The design entity becomes an instance in the testbench architecture.

>  I have found some text books
> that cover simulation testbenches and give a few examples. Very week though
> in terms of the numbers of examples and the strategy behind the use of the
> various commands. 

The basic strategy is to wiggle the inputs and watch
for expected values on the outputs.

> I still haven't found an example of a bidirectional test bench. 

here's one:
http://groups.google.com/groups?q=oe_demo+bidirectional+yang

Good luck.

       -- Mike Treseler

Brad Smallridge wrote:
> 
> Yeah. I am gathering that. And it is also difficult to understand where VHDL
> testbenches  "begins" and the other takes over. There is also a waveformer
> in the Xilinx tool that is somewhat intuitive. I have found some text books
> that cover simulation testbenches and give a few examples. Very week though
> in terms of the numbers of examples and the strategy behind the use of the
> various commands. I still haven't found an example of a bidirectional test
> bench.  I also started searching the web with the words downto and testbench
> and have found some examples, but these are not what I would call good
> tutorials.

Personally, I find a VHDL testbench much easier to write than generating
a waveform type stimulus.  In VHDL I can write procedures to control a
bus interface reading data from a file or provide feedback from one
external interface to another.  In short, it is a lot like writing any
other program since it does not need to be sythesizable.  

The *hard* part is knowing what you want it to do!  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Brad Smallridge wrote:

> Yeah. I am gathering that. And it is also difficult to understand where VHDL
> testbenches  "begins" and the other takes over. There is also a waveformer
> in the Xilinx tool that is somewhat intuitive. I have found some text books
> that cover simulation testbenches and give a few examples. Very week though
> in terms of the numbers of examples and the strategy behind the use of the
> various commands. I still haven't found an example of a bidirectional test
> bench.  I also started searching the web with the words downto and testbench
> and have found some examples, but these are not what I would call good
> tutorials.

IIRC the book "VHDL for Logic Synthesis" by Rushton has a good section 
on writing VHDL testbenches, talks about file IO and so on.

My preferred approach, when possible/sensible, is to write fairly 
generic VHDL testbenches that read the stimulus and expected response 
data from text files, and then drives the unit-under-test from that 
data.  This lets you use other tools to generate the input and output 
datasets.  I've used this to verify implementations of image processing 
algorithms - prototype the algorithm in matlab, design the hardware, 
then drive both the matlab and VHDL models with the same input data 
files, comparing the results.

Rgds,

John

> IIRC the book "VHDL for Logic Synthesis" by Rushton has a good section
> on writing VHDL testbenches, talks about file IO and so on.
>
> My preferred approach, when possible/sensible, is to write fairly
> generic VHDL testbenches that read the stimulus and expected response
> data from text files, and then drives the unit-under-test from that
> data.  This lets you use other tools to generate the input and output
> datasets.  I've used this to verify implementations of image processing
> algorithms - prototype the algorithm in matlab, design the hardware,
> then drive both the matlab and VHDL models with the same input data
> files, comparing the results.

This sounds like a powerful way to really check the video processing.
What kind of video processing are you doing? And what do the VHDL
models look like?

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Hi Brad,

Brad Smallridge wrote:

> This sounds like a powerful way to really check the video processing.
> What kind of video processing are you doing? And what do the VHDL
> models look like?

I'm sure it could be more powerful, but it met my needs.  I'm not doing 
a lot of video/image work now, this is from a few years ago when I was 
investigating some real-time remote sensing / image processing algorithms.

I've attached a sample test bench, maybe it will be useful in showing 
you the overall structure and file IO. It's not particularly 
sophisticated, but will give the general idea..

Regards,

John

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-- Vhdl test bench created from schematic conv_eng.sch - Wed May 22 11:00:13 2002
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE UNISIM.Vcomponents.ALL;
use ieee.std_logic_textio.all;

use std.textio.all;

use work.conv_types.all;

ENTITY testbench IS
END testbench;
ARCHITECTURE behavioral OF testbench IS 

   COMPONENT conv_eng
   PORT( clk	:	IN	STD_LOGIC; 
          d_strobe	:	IN	STD_LOGIC; 
          data_in	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          reset	:	IN	STD_LOGIC; 
          data_out	:	OUT	STD_LOGIC_VECTOR (15 DOWNTO 0); 
          oen	:	OUT	STD_LOGIC);
   END COMPONENT;

   SIGNAL clk	:	STD_LOGIC;
   SIGNAL d_strobe	:	STD_LOGIC;
   SIGNAL data_in	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   SIGNAL reset	:	STD_LOGIC;
   SIGNAL data_out	:	STD_LOGIC_VECTOR (15 DOWNTO 0);
   SIGNAL oen	:	STD_LOGIC;

   signal completed : std_logic;

   constant T_clk : time := 50 ns;
   constant T_su : time := 5 ns;
BEGIN

   UUT: conv_eng PORT MAP(
		clk => clk, 
		d_strobe => d_strobe, 
		data_in => data_in, 
		reset => reset, 
		data_out => data_out, 
		oen => oen
   );

   stimulus : PROCESS
     variable pix_cnt : integer := 0;
     variable pix_val : std_logic_vector(7 downto 0);
     variable clk_cnt : integer := 0;

     variable l_in : line;
     file infile : text open read_mode is "image.txt";

     procedure clock_cycle(signal clk : out std_logic) is
     begin
       wait for T_su;
       clk <= '1';
       wait for T_clk;
       clk <= '0';
       wait for T_clk-T_su;
     end procedure;

  BEGIN
    -- reset everything for a few clock cycles
    completed <= '0';
    d_strobe <= '0';
    reset <= '1';
    clock_cycle(clk);
    reset<= '0';
    clock_cycle(clk);

    -- run an image through the filter
    for row in 0 to rows-1 loop
      for col in 0 to cols-1 loop
        -- check for end of file
        assert not endfile(infile)
          report "Premature end of file!"
          severity failure;

        readline(infile,l_in);
        hread(l_in,pix_val);
			data_in <= pix_val;
        d_strobe <= '1';
        clock_cycle(clk);
        d_strobe <= '0';
        for clk_cnt in 0 to 12 loop
          clock_cycle(clk);
        end loop;
      end loop;
    end loop;

    -- drain the pipeline
    data_in <= (others => '0');
    for drain in 0 to cols loop
      d_strobe <= '1';
      clock_cycle(clk);
      d_strobe <= '0';
      for clk_cnt in 0 to 12 loop
        clock_cycle(clk);
      end loop;
    end loop;  
    
    completed <= '1';
    wait;

   END PROCESS;

   response:process
     variable l_out : line;
     file outfile : text open write_mode is "output.txt";

   begin
     wait on oen until oen'event and oen='1';
     if(completed='1') then
       wait;
     elsif(oen'event and oen='1') then
       hwrite(l_out,data_out);
       writeline(outfile,l_out);
     end if;
   end process;

END;

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