Low-power FPGAs?

Ray,

Yes, it just goes to show that you have to make some measurements to 
really discover everything.

Austin

Ray Andraka wrote:
> Faster and smaller generally comes out a little ahead of larger slower in my
> experience.  The trade off between clock speed and area is more or less a wash
> because power is proportional to clock frequency, however there are second
> order effects to consider.  First, a smaller design  means the routing can be
> more localized.  Routing distance is roughly proportional to the square root of
> the area.  Secondly, a parallel design, at least for arithmetic has extra
> routing orthogonal to the signal path and extra gating to handle the carry
> functions.  This extra logic and associated routing makes the v-F curve
> non-linear.
> 
> Austin Lesea wrote:
> 
> 
>>Hal,
>>
>>Let's see....P= CV^2F, and so for each node switching, the power scales
>>with frequency.
>>
>>One node at F is equal to two nodes at 1/2F?  Yes, it sure looks that way.
>>
>>I suppose the reason to run slower is to run cooler.
>>
>>But, you are right, run the smallest part as fast as needed to do the work.
>>
>>No reason to run it any faster than needed, however.
>>
>>One reason for the very low power for the DSP48 is that the capacitive
>>loads are very small.
>>
>>Good catch.
>>
>>Thanks,
>>
>>Austin
>>
>>Hal Murray wrote:
>>
>>
>>>>FPGAs are very efficient for doing the work (dynamic power), but high
>>>>clock speeds means lots of power.  Better to make the algorithm highly
>>>>parallel, and lower the clock rate as much as possible.
>>>
>>>
>>>What's going on here?  Classic reasoning says that 2 FFs at half
>>>speed will take the same power as 1 FF at full speed.  (assuming
>>>same cap load...)
>>>
>>>Why not run faster so you can use a smaller part and get lower
>>>static power?
>>>
> 
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
> 
> 

Jim,

Vccaux is required, as is Vcco for the config bank.

There is the Power On Reset control circuit wired to these three supply 
sources.  If the POR trips going low, then memory is zeroized when POR 
comes back up (On).

The static Icco is pretty low, I think less than 2 mA per bank (at 3.3V, 
less at a lower Vcco).  Still gathering data on that for the data sheet.

The proposal I heard (from one engineer) was to run all LVDS IO, with a 
few 2.5 V 2 mA CMOS single ended IOs for things like LEDs, switches, 
slow peripherals (like the power controller).

Turns out that LVDS IOs are constant 4mA each (hi or lo), so single 
ended IOs would be much more efficient (but slower).

The idea was to also go to the abs min voltages allowed for the sleep 
mode (e.g 1.0V), and the recommended mins for operation.

If that did not do it, they wanted to know if we would consider a test 
program to verify even lower sleep and operating voltages.

Good news is that the V4 is the most CMOS'sy chip we have had in awhile 
-- it really works well at lower voltages int eh interconnect, CLB and 
other simple functions.  The complex functions (MGT, DCM, PPC) are not 
likely to be as forgiving if run out of spec.

As I said before, test programs are just money, so if it is worthwhile, 
then it is considered.  We just need to be sure that we can yield 
reliably to the screen, and it makes business sense to do it.  It would 
not do anyone any good if the screen suddenly stopped yielding any parts 
due to a small process shift.  Such screens are never entered into 
lightly, and require a great deal of work (hence the reason why there is 
usually a large volume involved).

Often as we gain more data from a new part, we may change specifications 
(expand the operating ranges, speed up paths, etc.) so we will have to wait.

Austin



Jim Granville wrote:

> Austin Lesea wrote:

> <snip>
> 
>>
>> There is also Vccaux (Iccaux) at 2.5V, and Vcco at ??V to consider as 
>> well.
> 
> 
>  Only some devices have Vccaux - can that be removed, or does it need to 
> be reduced ?
>  Vcco I presume can be removed on selected banks, if you realled needed 
> to, but the Static Icc on IO cells should be very low, as they are
> relatively few - correct ?
> 
> -jg
> 

Hi Simon,
A few comments included below, but do we agree that saying "FPGA's by their
very nature are low power.. provided you don't clock them fast." is somewhat
misleading?
Cheers, Syms.

"Simon Peacock" <nowhere@to.be.found> wrote in message
news:417e23a9@news.actrix.gen.nz...
> Forget a V2PRO... unless you need a power PC... there are far cheaper
> options to get a processor.
>
> I also never suggested using bleeding edge... if you pick an 'older part'
> you will find the static current better... it just won't have the same
> capability as the modern 90 nm parts.. although cyclone (cough cough) seem
> to have a lower quiescent current 12mA - 80 mA.. but they probably cheated
> to get that.

The V2PRO I mentioned doesn't have a PowerPC, but anyway I'd question
whether V2PRO is bleeding edge. (Bleeding irritating, maybe!) Anyway, even
small plain old Virtex (50mA) and SpartanIIe (200mA) suffer from this
Iccintq problem. I'll check out the A parts, thanks for the pointer.

>
> And even tho A or X seems good what about Q ?
> Quicklogic Eclipse is a low power (not so) FPGA .. so they might be via
> OTP... so you prototype with RAM based... but you can't beat the 22 - 250
uA
> quiescent current... and only 100mA at 100Mhz.

Sounds like a good solution.

>
> Don't forget the option of powering down when not in use, use a coolrunner
> to turn the FPGA off if necessary / possible just don't forget to shut
down
> I/O too.. or the saving will be killed by protection diodes.
> Older FPGA's have smaller configurations and can be programmed fast if you
> externally clock them.
>

So, if the CPLD/FPGA you're powering down has live inputs from other places,
won't these inputs back power the part through the protection diodes? So,
the inputs have to be off too?

> And yea.. design to typical.. select of test even :-) unless your running

You bad boy! I'd never do that. (= I'd never admit to doing that!) ;-)

>
> at -20 or +60C .. but at 0C you NiMH battery life will be half that at 20C
> too..
> Then pick a better battery... heard of lithium ion? :-)

What do you mean by better? Price? Also, Lion and NiMH have the same(ish)
volumetric energy density. Are Lions better over temperature? Is self
discharge better in Lions? (Sounds like a sticky mess in the Serengeti!)

> You might also want to watch the D cells.. often the are a 'C' cell in
side
> a cardboard wrapper.  There are also special 'radio modeller' NiCAD's that
> have rather nice mAH ratings... designed for electric cars and planes.
>

I thought these special NiCds were high power cells, not high energy?

> I have a battery pack here good for 600mA hours @ 8.4V... not much bigger
> than a D cell.

Which is why it has the same(ish) energy storage as a NiMH D cell! 6.5Ah @
1.2V.
http://www.panasonic.com/industrial/battery/oem/
>
> Simon
>
>
>
> "Symon" <symon_brewer@hotmail.com> wrote in message
> news:2u4nrqF26i2edU1@uni-berlin.de...
> > Simon,
> > I guess it's been a while since you checked out the quiescent supply
> > currents for the latest parts? For example, worst case Iccintq for the
> > smallest V2PRO (XC2VP2) is 300mA. That's about 20 hours on a NiMH D
cell.
> > Typical is 20mA, but no-one would design with typical figures, would
they?
> > BTW, anyone know why there's such a big difference from 'typical' to
'max'
> > figures? Does it depend on the configuration used in the part?
> > Cheers, Syms.
> >
> > "Simon Peacock" <nowhere@to.be.found> wrote in message
> > news:417cd164@news.actrix.gen.nz...
> > > FPGA's by their very nature are low power.. provided you don't clock
> them
> > > fast.
> > >
> >
> >
> >
>
>

Austin Lesea wrote:

> Jim,
> 
> Vccaux is required, as is Vcco for the config bank.

Power of VccAux ?
Are you saying Non-config banks can be Vcco removed, if desired ?
[eg a DRAM interface could de-power the DRAMS, and their Banks ?]

> 
> There is the Power On Reset control circuit wired to these three supply 
> sources.  If the POR trips going low, then memory is zeroized when POR 
> comes back up (On).
> 
> The static Icco is pretty low, I think less than 2 mA per bank (at 3.3V, 
> less at a lower Vcco).  Still gathering data on that for the data sheet.
> 
> The proposal I heard (from one engineer) was to run all LVDS IO, with a 
> few 2.5 V 2 mA CMOS single ended IOs for things like LEDs, switches, 
> slow peripherals (like the power controller).
> 
> Turns out that LVDS IOs are constant 4mA each (hi or lo), so single 
> ended IOs would be much more efficient (but slower).
> 
> The idea was to also go to the abs min voltages allowed for the sleep 
> mode (e.g 1.0V), and the recommended mins for operation.
> 
> If that did not do it, they wanted to know if we would consider a test 
> program to verify even lower sleep and operating voltages.
> 
> Good news is that the V4 is the most CMOS'sy chip we have had in awhile 
> -- it really works well at lower voltages int eh interconnect, CLB and 
> other simple functions.  The complex functions (MGT, DCM, PPC) are not 
> likely to be as forgiving if run out of spec.
> 
> As I said before, test programs are just money, so if it is worthwhile, 
> then it is considered.  We just need to be sure that we can yield 
> reliably to the screen, and it makes business sense to do it.  It would 
> not do anyone any good if the screen suddenly stopped yielding any parts 
> due to a small process shift.  Such screens are never entered into 
> lightly, and require a great deal of work (hence the reason why there is 
> usually a large volume involved).
> 
> Often as we gain more data from a new part, we may change specifications 
> (expand the operating ranges, speed up paths, etc.) so we will have to 
> wait.

  This is sounding a good direction, similar to Mobile Pentiums/Athlons.
There are SMPS devices with quite wide binary control of Vout, designed 
for the CPU markets.

Also, devices like the new LTC6905
http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1010,C1096,P7888
also has power-save promise, by clock-vary 17:170MHz at reasonably low 
power levels.

  Most small micropower uC have clock-out options, that can also be used
if some portion of the FPGA needs to 'tick-over' - I think from what you
are saying, that the complex blocks, DLLs etc do not work as low as
the logic fabric, and config SRAMs - so something like an LCD interface,
or a keypad scan could run at < 1MHz at the lower Vccs ?
  [ that would allow users to choose between a really small uC, and
some sytem IO in the FPGA, or a larger uC with more pins, and more
agressive power-removals on the FPGA. ]


-jg

Jim,

Yes, if all you want to do is 'sleep', you can remove power from the 
Vcco banks other than the one with the POR circuit on it.

The intrinsic protection diodes are always there, so if other circuits 
are powered, you may end up powering the Vcco of the banks through the 
diodes.

Austin



Jim Granville wrote:
> Austin Lesea wrote:
> 
>> Jim,
>>
>> Vccaux is required, as is Vcco for the config bank.
> 
> 
> Power of VccAux ?
> Are you saying Non-config banks can be Vcco removed, if desired ?
> [eg a DRAM interface could de-power the DRAMS, and their Banks ?]
> 
>>
>> There is the Power On Reset control circuit wired to these three 
>> supply sources.  If the POR trips going low, then memory is zeroized 
>> when POR comes back up (On).
>>
>> The static Icco is pretty low, I think less than 2 mA per bank (at 
>> 3.3V, less at a lower Vcco).  Still gathering data on that for the 
>> data sheet.
>>
>> The proposal I heard (from one engineer) was to run all LVDS IO, with 
>> a few 2.5 V 2 mA CMOS single ended IOs for things like LEDs, switches, 
>> slow peripherals (like the power controller).
>>
>> Turns out that LVDS IOs are constant 4mA each (hi or lo), so single 
>> ended IOs would be much more efficient (but slower).
>>
>> The idea was to also go to the abs min voltages allowed for the sleep 
>> mode (e.g 1.0V), and the recommended mins for operation.
>>
>> If that did not do it, they wanted to know if we would consider a test 
>> program to verify even lower sleep and operating voltages.
>>
>> Good news is that the V4 is the most CMOS'sy chip we have had in 
>> awhile -- it really works well at lower voltages int eh interconnect, 
>> CLB and other simple functions.  The complex functions (MGT, DCM, PPC) 
>> are not likely to be as forgiving if run out of spec.
>>
>> As I said before, test programs are just money, so if it is 
>> worthwhile, then it is considered.  We just need to be sure that we 
>> can yield reliably to the screen, and it makes business sense to do 
>> it.  It would not do anyone any good if the screen suddenly stopped 
>> yielding any parts due to a small process shift.  Such screens are 
>> never entered into lightly, and require a great deal of work (hence 
>> the reason why there is usually a large volume involved).
>>
>> Often as we gain more data from a new part, we may change 
>> specifications (expand the operating ranges, speed up paths, etc.) so 
>> we will have to wait.
> 
> 
>  This is sounding a good direction, similar to Mobile Pentiums/Athlons.
> There are SMPS devices with quite wide binary control of Vout, designed 
> for the CPU markets.
> 
> Also, devices like the new LTC6905
> http://www.linear.com/pc/productDetail.do?navId=H0,C1,C1010,C1096,P7888
> also has power-save promise, by clock-vary 17:170MHz at reasonably low 
> power levels.
> 
>  Most small micropower uC have clock-out options, that can also be used
> if some portion of the FPGA needs to 'tick-over' - I think from what you
> are saying, that the complex blocks, DLLs etc do not work as low as
> the logic fabric, and config SRAMs - so something like an LCD interface,
> or a keypad scan could run at < 1MHz at the lower Vccs ?
>  [ that would allow users to choose between a really small uC, and
> some sytem IO in the FPGA, or a larger uC with more pins, and more
> agressive power-removals on the FPGA. ]
> 
> 
> -jg
> 
> 

I probably am misleading some what... but experience for a typical design is
FPGA's don't consume much.  they are usually the lowest power consumer on my
designs.  but done right....  An FPGA will draw less power than a micro
doing the same thing.  the last card had a dynamic current in the FPGA of
about 8 mA (excluding I/O) that's according the power calculator and the
interface it connected to could draw 2amps.  I don't think that's too bad.

And I usually do design to the spec... we rate our radios from  -10C to +65C
and aren't allowed more than 2 'noise' hits over a temperature cycle.  But
for a piece of test gear sitting on a bench.. I think you can go slightly
wild and limit the temperature range... unless you going to sit it in a shed
in a desert... which I doubt.

I saw your battery... not bad... but usually higher voltages win out over
higher amp-hour... at low voltages the switcher losses become silicon volt
drop related.  If you look at Maxium you will see they quite often invert
the voltage and then switch up from the sum of the voltages to get the
efficiency up when working with low voltages.

Am glad you like the Q FPGA.  I came across it while helping design a
satellite here.  Its fuse link, no free tools, no free programmer... so I
would defiantly prototype with something else until you can be assured of it
working.

For driving a FPGA from a CPLD.. you might need an interface IC in between.
There are a number of logic families that support hot-swap which should stop
any current draw when the chip is in power down.. failing that.. 10k
resisters are pretty good too :-)
Or you could make sure all devices drive the FPGA with a low by default...
then there is no power for the protection diodes to suck :-)

Simon


"Symon" <symon_brewer@hotmail.com> wrote in message
news:2u7hb2F25pfq8U1@uni-berlin.de...
> Hi Simon,
> A few comments included below, but do we agree that saying "FPGA's by
their
> very nature are low power.. provided you don't clock them fast." is
somewhat
> misleading?
> Cheers, Syms.
>
> "Simon Peacock" <nowhere@to.be.found> wrote in message
> news:417e23a9@news.actrix.gen.nz...
> > Forget a V2PRO... unless you need a power PC... there are far cheaper
> > options to get a processor.
> >
> > I also never suggested using bleeding edge... if you pick an 'older
part'
> > you will find the static current better... it just won't have the same
> > capability as the modern 90 nm parts.. although cyclone (cough cough)
seem
> > to have a lower quiescent current 12mA - 80 mA.. but they probably
cheated
> > to get that.
>
> The V2PRO I mentioned doesn't have a PowerPC, but anyway I'd question
> whether V2PRO is bleeding edge. (Bleeding irritating, maybe!) Anyway, even
> small plain old Virtex (50mA) and SpartanIIe (200mA) suffer from this
> Iccintq problem. I'll check out the A parts, thanks for the pointer.
>
> >
> > And even tho A or X seems good what about Q ?
> > Quicklogic Eclipse is a low power (not so) FPGA .. so they might be via
> > OTP... so you prototype with RAM based... but you can't beat the 22 -
250
> uA
> > quiescent current... and only 100mA at 100Mhz.
>
> Sounds like a good solution.
>
> >
> > Don't forget the option of powering down when not in use, use a
coolrunner
> > to turn the FPGA off if necessary / possible just don't forget to shut
> down
> > I/O too.. or the saving will be killed by protection diodes.
> > Older FPGA's have smaller configurations and can be programmed fast if
you
> > externally clock them.
> >
>
> So, if the CPLD/FPGA you're powering down has live inputs from other
places,
> won't these inputs back power the part through the protection diodes? So,
> the inputs have to be off too?
>
> > And yea.. design to typical.. select of test even :-) unless your
running
>
> You bad boy! I'd never do that. (= I'd never admit to doing that!) ;-)
>
> >
> > at -20 or +60C .. but at 0C you NiMH battery life will be half that at
20C
> > too..
> > Then pick a better battery... heard of lithium ion? :-)
>
> What do you mean by better? Price? Also, Lion and NiMH have the same(ish)
> volumetric energy density. Are Lions better over temperature? Is self
> discharge better in Lions? (Sounds like a sticky mess in the Serengeti!)
>
> > You might also want to watch the D cells.. often the are a 'C' cell in
> side
> > a cardboard wrapper.  There are also special 'radio modeller' NiCAD's
that
> > have rather nice mAH ratings... designed for electric cars and planes.
> >
>
> I thought these special NiCds were high power cells, not high energy?
>
> > I have a battery pack here good for 600mA hours @ 8.4V... not much
bigger
> > than a D cell.
>
> Which is why it has the same(ish) energy storage as a NiMH D cell! 6.5Ah @
> 1.2V.
> http://www.panasonic.com/industrial/battery/oem/
> >

Simon,
I saw this article and thought of our musings about low power stuff!
http://www.reed-electronics.com/electronicnews/article/CA475494?nid=2019&rid=1090846109
"Royal Philips Electronics� Handshake Solutions and ARM today said they have
jointly developed a clockless, compact ARM processor to addresses (sic) low
power consumption"
It's based on this stuff
http://www.cs.man.ac.uk/apt/projects/processors/amulet/
http://www.cs.man.ac.uk/apt/projects/processors/amulet/AMULET3i_seminar.pdf
I wonder if self-timed circuits will come to the FPGA world soon? A whole
new level of pain!
Best, Syms.

Symon wrote:
> Simon,
> I saw this article and thought of our musings about low power stuff!
> http://www.reed-electronics.com/electronicnews/article/CA475494?nid=2019&rid=1090846109
> "Royal Philips Electronics� Handshake Solutions and ARM today said they have
> jointly developed a clockless, compact ARM processor to addresses (sic) low
> power consumption"
> It's based on this stuff
> http://www.cs.man.ac.uk/apt/projects/processors/amulet/
> http://www.cs.man.ac.uk/apt/projects/processors/amulet/AMULET3i_seminar.pdf
> I wonder if self-timed circuits will come to the FPGA world soon? A whole
> new level of pain!

  Interesting - Philips have been doing Async logic for a while, 
including Async 80C51 variants, and have the important tools needed to 
design in this area.

  Advantages are self-tracking of temp and Vcc, allowing wider operating
tolerance. Power numbers I've seen for their earlier devices were good,
but not stellar, but did improve rapidly as Vcc decreased.
  FPGAs could use this, with the right tools.
-jg

Hi Jim,
Indeed, looks like some folks are thinking about this in FPGAs already.
Check out
http://www.opencores.org/articles.cgi/view/28
http://vlsi.cornell.edu/fpga.php
http://www.async.caltech.edu/Pubs/PDF/
etc....
Cheers, Syms.

"Jim Granville" <no.spam@designtools.co.nz> wrote in message 
news:SL_fd.23542$mZ2.871764@news02.tsnz.net...
>  Interesting - Philips have been doing Async logic for a while, including 
> Async 80C51 variants, and have the important tools needed to design in 
> this area.
>
>  Advantages are self-tracking of temp and Vcc, allowing wider operating
> tolerance. Power numbers I've seen for their earlier devices were good,
> but not stellar, but did improve rapidly as Vcc decreased.
>  FPGAs could use this, with the right tools.
> -jg
> 

>> And yea.. design to typical.. select of test even :-) unless your running
>You bad boy! I'd never do that. (= I'd never admit to doing that!) ;-)

There is an art to reading between the lines on a data sheet.
Or maybe knowing which lines you can read between.

If leakage current is critical, the difference between a warm room
and 85C or 100C is huge.  Consider the CPU in the remote control
for your TV.  What's its temperature?  Are you going to compute
battery life based on storing it in an oven?

If you are only buying a few chips, you can measure them yourself.
If you are placing a big order, you can get lots of help from FAEs.


A few generations ago, it used to be common to fudge ratings by
"correcting" for VCC and temperature.  If you were willing to work
a bit harder on your power supply, say promise it won't go below
nominal, then you could pick up 5% on speed.  Old Xilinx data books
had a nice writeup.  I'm pretty sure DEC did that with their high
end Alphas.

Then the silicon wizards made things more complicated.  I don't
understand the details but I'll bet it's an interesting story.

I think the simple exponential temperature correction still holds
for leakage current. Can anybody confirm that?  (Any predictions
on when that will break?  Why?)

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