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PLL Clocks on Cyclone Devices

Started by Jock October 25, 2004
Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V -
i.e. what is the maximum rise time on the edge of the PLL clock input?


Jock wrote:

> Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V - > i.e. what is the maximum rise time on the edge of the PLL clock input?
What is wrong with a line receiver to meet the AC voltage specifications ? The 1.5V-IO requires 0.35 and 0.65 times 1.5V as levels. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
"Rene Tschaggelar" <none@none.net> wrote in message
news:417d4fca$0$28024$5402220f@news.sunrise.ch...
> Jock wrote: > > > Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V - > > i.e. what is the maximum rise time on the edge of the PLL clock input? > > What is wrong with a line receiver to meet the AC voltage > specifications ? > The 1.5V-IO requires 0.35 and 0.65 times 1.5V as levels. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net
We don't have a lot of real estate and I was looking at ways of reducing component count.