I am interested in safety for embedded applications. So I read this articels dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 with great interest. People listed a lot of advantages of FPGAs, however the major problem (related to safety) left was that the FPGA has to be reprogrammed at each power up. My question: isn't an CPLD a good solution for small safety critical applications? Falk ---------------------------------------------------------- Chair of Computer Science XI RWTH Aachen University Germany
CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
Started by ●October 29, 2004
Reply by ●October 29, 20042004-10-29
Could you post a link to the original article? There are lots more concerns other than the reprogramming. One such thing is the effect of Single Event Upsets. For example, configuration bits of the FPGA/CPLD can be flipped by SEUs (even at sea-level this is more important than MTBF) making the logic you designed behave incorrectly. Of course mitigation techniques exist, such as Triple Mode Redundancy, (and Device read-back and reconfiguration for some devices) Having said that CPLDs are much smaller devices, often at higher internal voltages, hence don't have the same problems with MTTE. If your system is small enough, and can be made fully redundant to cover MTBF failures, CPLD would be my advice. You want to check out the IEC-61508 Standard, and the Xilinx Military applications page. (or http://lhc-mpwg-reliability.web.cern.ch/lhc%2Dmpwg%2Dreliability/) HTH Ben "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message news:2uee97F28fi9jU1@uni-berlin.de...> I am interested in safety for embedded applications. So I read thisarticels> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 > with great interest. > > People listed a lot of advantages of FPGAs, however the major problem > (related to safety) left was that the FPGA has to be reprogrammed at each > power up. > > My question: isn't an CPLD a good solution for small safety critical > applications? > > Falk > ---------------------------------------------------------- > Chair of Computer Science XI > RWTH Aachen University > Germany > >
Reply by ●October 29, 20042004-10-29
Thanks for the reply! I got the original article from http://www.fpga-faq.com/archives/04700.html#4721 You can find there the problem you mentioned, too. I was just wondering if a CPLD would meet safety requirements better than a FPGA. Falk "Benjamin Todd" <benjamin.toddnospam@cern.ch> schrieb im Newsbeitrag news:clt313$3or$1@sunnews.cern.ch...> Could you post a link to the original article? > > There are lots more concerns other than the reprogramming. One such thing > is the effect of Single Event Upsets. > For example, configuration bits of the FPGA/CPLD can be flipped by SEUs > (even at sea-level this is more important than MTBF) making the logic you > designed behave incorrectly. > > Of course mitigation techniques exist, such as Triple Mode Redundancy, > (and > Device read-back and reconfiguration for some devices) > > Having said that CPLDs are much smaller devices, often at higher internal > voltages, hence don't have the same problems with MTTE. If your system is > small enough, and can be made fully redundant to cover MTBF failures, CPLD > would be my advice. > > You want to check out the IEC-61508 Standard, and the Xilinx Military > applications page. > (or http://lhc-mpwg-reliability.web.cern.ch/lhc%2Dmpwg%2Dreliability/) > HTH > Ben > > > > > "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message > news:2uee97F28fi9jU1@uni-berlin.de... >> I am interested in safety for embedded applications. So I read this > articels >> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 >> with great interest. >> >> People listed a lot of advantages of FPGAs, however the major problem >> (related to safety) left was that the FPGA has to be reprogrammed at each >> power up. >> >> My question: isn't an CPLD a good solution for small safety critical >> applications? >> >> Falk >> ---------------------------------------------------------- >> Chair of Computer Science XI >> RWTH Aachen University >> Germany >> >> > >
Reply by ●October 29, 20042004-10-29
Let's keep things in pespective. Yes, "SRAM-based" FPGAs can be upset by random SEUs. But how likely is this? We at Xilinx have done extensive real-time tests with thousands of large devices (XC2V6000) over more than a year, and here is a snapshot of the result: A device of Virtex-II 1000 complexity ( "1 million FPGA gates") is likely to pick up a functional error due to SEU roughly once per thousand years of operation. The much smaller XC2V40 is about twice the complexity of the largest CPLD, and it would encounter a functional error once per 25000 years. That's a pretty good MTBF. Better than the FIT rate of many other, even passive, coponents. Peter Alfke, Xilinx Applications =====================> From: "Benjamin Todd" <benjamin.toddnospam@cern.ch> > Organization: CERN - European Laboratory for Particle Physics > Newsgroups: comp.arch.fpga > Date: Fri, 29 Oct 2004 11:37:38 +0200 > Subject: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps. > > Could you post a link to the original article? > > There are lots more concerns other than the reprogramming. One such thing > is the effect of Single Event Upsets. > For example, configuration bits of the FPGA/CPLD can be flipped by SEUs > (even at sea-level this is more important than MTBF) making the logic you > designed behave incorrectly. > > Of course mitigation techniques exist, such as Triple Mode Redundancy, (and > Device read-back and reconfiguration for some devices) > > Having said that CPLDs are much smaller devices, often at higher internal > voltages, hence don't have the same problems with MTTE. If your system is > small enough, and can be made fully redundant to cover MTBF failures, CPLD > would be my advice. > > You want to check out the IEC-61508 Standard, and the Xilinx Military > applications page. > (or http://lhc-mpwg-reliability.web.cern.ch/lhc%2Dmpwg%2Dreliability/) > HTH > Ben > > > > > "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message > news:2uee97F28fi9jU1@uni-berlin.de... >> I am interested in safety for embedded applications. So I read this > articels >> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 >> with great interest. >> >> People listed a lot of advantages of FPGAs, however the major problem >> (related to safety) left was that the FPGA has to be reprogrammed at each >> power up. >> >> My question: isn't an CPLD a good solution for small safety critical >> applications? >> >> Falk >> ---------------------------------------------------------- >> Chair of Computer Science XI >> RWTH Aachen University >> Germany >> >> > >
Reply by ●October 29, 20042004-10-29
Apparently, some CPLD's get reprogrammed after each power cycle. There is at least one where the programmed bits are stored in non-volatile flash, but program RAM LUT's(?) upon powerup that is transparent to the user. I would suspect that the CPLD RAM values are susceptable just like RAM based FPGA's, but that is only a guess on my part. "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message news:<2uee97F28fi9jU1@uni-berlin.de>...> I am interested in safety for embedded applications. So I read this articels > dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 > with great interest. > > People listed a lot of advantages of FPGAs, however the major problem > (related to safety) left was that the FPGA has to be reprogrammed at each > power up. > > My question: isn't an CPLD a good solution for small safety critical > applications? > > Falk > ---------------------------------------------------------- > Chair of Computer Science XI > RWTH Aachen University > Germany
Reply by ●November 2, 20042004-11-02
Is this reliability data availible? Can I find it in your Xilinx Device Reliability Report? And still there is the question, if CPLDs might have a higher reliability than FPGAs. Falk "Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:BDA7AF5C.99DE%peter@xilinx.com...> Let's keep things in pespective. > Yes, "SRAM-based" FPGAs can be upset by random SEUs. But how likely is > this? > We at Xilinx have done extensive real-time tests with thousands of large > devices (XC2V6000) over more than a year, and here is a snapshot of the > result: > A device of Virtex-II 1000 complexity ( "1 million FPGA gates") is likely > to > pick up a functional error due to SEU roughly once per thousand years of > operation. > The much smaller XC2V40 is about twice the complexity of the largest CPLD, > and it would encounter a functional error once per 25000 years. > That's a pretty good MTBF. Better than the FIT rate of many other, even > passive, coponents. > Peter Alfke, Xilinx Applications > ===================== >> From: "Benjamin Todd" <benjamin.toddnospam@cern.ch> >> Organization: CERN - European Laboratory for Particle Physics >> Newsgroups: comp.arch.fpga >> Date: Fri, 29 Oct 2004 11:37:38 +0200 >> Subject: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical >> Apps. >> >> Could you post a link to the original article? >> >> There are lots more concerns other than the reprogramming. One such >> thing >> is the effect of Single Event Upsets. >> For example, configuration bits of the FPGA/CPLD can be flipped by SEUs >> (even at sea-level this is more important than MTBF) making the logic you >> designed behave incorrectly. >> >> Of course mitigation techniques exist, such as Triple Mode Redundancy, >> (and >> Device read-back and reconfiguration for some devices) >> >> Having said that CPLDs are much smaller devices, often at higher internal >> voltages, hence don't have the same problems with MTTE. If your system is >> small enough, and can be made fully redundant to cover MTBF failures, >> CPLD >> would be my advice. >> >> You want to check out the IEC-61508 Standard, and the Xilinx Military >> applications page. >> (or http://lhc-mpwg-reliability.web.cern.ch/lhc%2Dmpwg%2Dreliability/) >> HTH >> Ben >> >> >> >> >> "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote in message >> news:2uee97F28fi9jU1@uni-berlin.de... >>> I am interested in safety for embedded applications. So I read this >> articels >>> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around >>> 1996 >>> with great interest. >>> >>> People listed a lot of advantages of FPGAs, however the major problem >>> (related to safety) left was that the FPGA has to be reprogrammed at >>> each >>> power up. >>> >>> My question: isn't an CPLD a good solution for small safety critical >>> applications? >>> >>> Falk >>> ---------------------------------------------------------- >>> Chair of Computer Science XI >>> RWTH Aachen University >>> Germany >>> >>> >> >> >
Reply by ●November 3, 20042004-11-03
"Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote:> I am interested in safety for embedded applications. So I read this articels > dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 > with great interest. > > People listed a lot of advantages of FPGAs, however the major problem > (related to safety) left was that the FPGA has to be reprogrammed at each > power up. > > My question: isn't an CPLD a good solution for small safety critical > applications?What principle advantage do you think to gain with an CPLD over an FPGA? If you think about a flash based CPLD, why not using a flash based FPGA? A lot of Hi-Rel applications use fuse-based fpgas which are (almost) immune against functional changes after programming and are ready to start after power-up. So you end nearly in a safety level you reach with asics. bye Thomas
Reply by ●November 3, 20042004-11-03
Didn't know about flash based FPGAs before. Maybe it's something to think about. Thanks for your reply! Falk "Thomas Stanka" <usenet_10@stanka-web.de> schrieb im Newsbeitrag news:ef424d2c.0411022357.68e94613@posting.google.com...> "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote: >> I am interested in safety for embedded applications. So I read this >> articels >> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 >> with great interest. >> >> People listed a lot of advantages of FPGAs, however the major problem >> (related to safety) left was that the FPGA has to be reprogrammed at each >> power up. >> >> My question: isn't an CPLD a good solution for small safety critical >> applications? > > What principle advantage do you think to gain with an CPLD over an > FPGA? > If you think about a flash based CPLD, why not using a flash based > FPGA? > > A lot of Hi-Rel applications use fuse-based fpgas which are (almost) > immune against functional changes after programming and are ready to > start after power-up. So you end nearly in a safety level you reach > with asics. > > bye Thomas
Reply by ●November 3, 20042004-11-03
Falk Salewski wrote:> > Didn't know about flash based FPGAs before. Maybe it's something to think > about. > Thanks for your reply!The ones I have seen are actually SRAM FPGAs with an automatic loader from on-chip flash. This loads much faster than an external flash would, but otherwise the process is the same. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●November 4, 20042004-11-04
rickman <spamgoeshere4@yahoo.com> wrote> Falk Salewski wrote: > > > > Didn't know about flash based FPGAs before. Maybe it's something to think > > about. > > Thanks for your reply! > > The ones I have seen are actually SRAM FPGAs with an automatic loader > from on-chip flash. This loads much faster than an external flash > would, but otherwise the process is the same.As far as I know, are Actel ProAsic Plus not SRAM-Cells with on-chip flash. Of course there are SRAM-Cells for embedded RAM, but the logic itself seems to be stored in flash technology. The only fpga I unterstood using SRAM-logic with on-chip flash are lattice Fpgas. But feel free to correct me, I like to learn something new :=). bye Thomas
