chipscope pro problem (par)

I'm experimenting with chipscope pro to test it and see if we can use it in
our company, so i got the 6.3i demo and am inserting the ILA/ICON and VIO
and in the  PAR report i get:

WARNING:Place -
   The structured logic associated with a shift register could not be placed
in
   such a way as to use the appropriate fast connections.  Shift registers
   should flow through every slice down through the clb(s) that they use.
The
   relative placement required by the logic was impossible to resolve.

The following components are involved in this logic:
  SLICE
i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m
atch
/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxh/O
  SLICE
i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m
atch
/pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O
  SLICE
i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m
atch
/pd_rpm/i_tw_gte8/f_tw/0/i_yes_rpm/u_muxh/O
This situation can be resolved by fixing the following issue:

The structured logic could not be placed in the relative placement form
required.  This is due to the fact that the component
i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m
atch
/pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O is already contained in an rpm
that
will not allow the logic to be placed in the legal form.

WARNING:Place -
   The structured logic associated with a shift register could not be placed
in
   such a way as to use the appropriate fast connections.  Shift registers
   should flow through every slice down through the clb(s) that they use.
The
   relative placement required by the logic was impossible to resolve.

The following components are involved in this logic:
  SLICE
i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m
atch
/pd_rpm/i_twmod8_ne0/i_yes_rpm/u_muxh/O
  SLICE
i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m
atch
/pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O
This situation can be resolved by fixing the following issue:

The structured logic could not be placed in the relative placement form
required.  This is due to the fact that the component
i_ila_test/ila_test/i_no_d/u_ila/u_trig/u_tm/g_nmu/4/u_m/u_mu/i_mut_gand/u_m
atch
/pd_rpm/i_tw_gte8/f_tw/1/i_yes_rpm/u_muxh/O is already contained in an rpm
that
will not allow the logic to be placed in the legal form.

now i was wondering, is this a fault in my implementation of a mistake by
the chipscope generator? Thanks in advanca

kind regards

"Yttrium" <Yttrium@pandora.be> wrote in message
news:wRuid.11510$Hh1.459812@phobos.telenet-ops.be...
> I'm experimenting with chipscope pro to test it and see if we can use it
in
> our company, so i got the 6.3i demo and am inserting the ILA/ICON and VIO
> and in the  PAR report i get:
>
> WARNING:Place -
>    The structured logic associated with a shift register could not be
placed
> in

just dont pay attention to that, it always gives zillion of similar
warnings!

advice: if you do any serious FPGA verification (with Xilinx silicon) you
*MUST* use ChipScope - no way around it. There are other OCI solutions
availabe of course also, but I would defenetly consider ChipScope as primary
tool.

Antti

PS I am using ChipScope to to capture at 3GS/S :)
with rocketIO and custom "analyzer" application, kinda nice to see 3GS/S
Logic analyzer - my primary use was capturing USB HS raw data, V2Pro
rocketio can be directly coupled to USB (receive only)...

Anyone looked at or using Synplicity's Identify product? Wanna share your
experiences?
Cheers, Syms.

Antti Lukats a �crit:

> advice: if you do any serious FPGA verification (with Xilinx silicon) you
> *MUST* use ChipScope - no way around it. There are other OCI solutions
> availabe of course also, but I would defenetly consider ChipScope as primary
> tool.

I still wonder why Xilinx is *selling* this tool, especially since you 
can't do much serious work without it.
Altera's SignalTap is free and (IMO) much more user friendly.

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"Symon" <symon_brewer@hotmail.com> wrote in message
news:2uve7mF2es7aoU1@uni-berlin.de...
> Anyone looked at or using Synplicity's Identify product? Wanna share your
> experiences?
> Cheers, Syms.
:) yes looked only shortly, its more like "rtl debugger" not logic analyzer.
A nice tool in any case that for sure. Unfortunatly our free license expired
before I had any chance to test any further. Its funny, they Identify lite
is supposed to be free, but after registration they will try to call your
mobile, and the free license expires very quickly.

Antti

"Nicolas Matringe" <matringe.nicolas@numeri-cable.fr> wrote in message
news:418B3A65.9040700@numeri-cable.fr...
> Antti Lukats a &#4294967295;crit:
>
> > advice: if you do any serious FPGA verification (with Xilinx silicon)
you
> > *MUST* use ChipScope - no way around it. There are other OCI solutions
> > availabe of course also, but I would defenetly consider ChipScope as
primary
> > tool.
>
> I still wonder why Xilinx is *selling* this tool, especially since you
> can't do much serious work without it.
> Altera's SignalTap is free and (IMO) much more user friendly.

You are right - it would much nicer if ChipScope would be free (at least for
those who have ISE full...) I got ChipScope initially as bundled software
with ML300 (total value of purchase >$5000 USD), that CS was version 5.1 and
there was no free update to even 5.2 !! That was bizarre! And the price went
up 2 times what also isnt so nice change. I guess the reason Xilinx is
selling ChipScope is that ChipScope cores, including ILA (not only ATC2) -
are designed by Agilent, so there could be still some ownership issue. This
information is (about who wrote ILA cores) is from inside Agilent so I
assume its correct. Possible that also explains why the core integration
isnt always working as smootly as it could be and why Xilinx still is
struggling to get Chipscope analyzer to work in Linux.

I have used ChipScope for long time, and sure have a lot of struggle with
it. Its getting better with every service pack. And if you KNOW it you can
use it in very friendly manner. If you dont, well then you have to learn,
possible the hard way.

I dont want to say that, but when I first time tested SignalTap - I was
really surprised how easy it was! Funny thing is that I used SignalTap to
check out how MicroBlaze works in Cyclone :)
ok, YES, SignalTap is easy (its not directly free as you need use it on a PC
that is required to be online and sends reports back to Altera), SignalTap
doesnt have some features that I use in ChipScope VIO and core generator are
not there.

Hm, another thing that is missing from ChipScope is upload of user memories!
(SignalTap can do that).

ok, enough :)
Antti
PS I still have a dream of doing a cross platform OCI system some day
(partial work is completed)

Nicolas Matringe wrote:
> Antti Lukats a �crit:
> 
>> advice: if you do any serious FPGA verification (with Xilinx silicon) you
>> *MUST* use ChipScope - no way around it. There are other OCI solutions
>> availabe of course also, but I would defenetly consider ChipScope as 
>> primary tool.

> I still wonder why Xilinx is *selling* this tool, especially since you 
> can't do much serious work without it.
> Altera's SignalTap is free and (IMO) much more user friendly.

It is possible to do serious work without
ChipScope or SignalTap, but it requires synchronous
design and continuous simulation and regression testing.

           -- Mike Treseler

"Mike Treseler" <mike_treseler@comcast.net> wrote in message
news:ktadnfExOLKmERbcRVn-jQ@comcast.com...
> Nicolas Matringe wrote:
> > Antti Lukats a &#4294967295;crit:
> >
> >> advice: if you do any serious FPGA verification (with Xilinx silicon)
you
> >> *MUST* use ChipScope - no way around it. There are other OCI solutions
> >> availabe of course also, but I would defenetly consider ChipScope as
> >> primary tool.
>
> > I still wonder why Xilinx is *selling* this tool, especially since you
> > can't do much serious work without it.
> > Altera's SignalTap is free and (IMO) much more user friendly.
>
> It is possible to do serious work without
> ChipScope or SignalTap, but it requires synchronous
> design and continuous simulation and regression testing.
>
>            -- Mike Treseler

Hi Mike,

I was already wondering who will reply and say that he can do all by
simulations only :)
Sure it is possible todo it all without the use of any OnChipInstrumentation
tools at all.

But if you work with external ASIC PHY test chips without even having proper
timing specs for those or in case the latency specs for the external phy
chips are wrong, then well you just cant simulate what you do not know, you
need to see whats happening inside the FPGA. Maybe my experiences are not
common and everybody else are very happy with simulations only, but I have
found ChipScope and its advanced use of very great value, and it has been
able todo many things that would not be possible or would have taken too
much time.

Like RocketIO has some gotchas, and the simulation models are not good
enough, so by doing simulations only you can not get a Serial OOB detect
circuitry working. No way. Because rocketio receives random noise with 4
bits repeating pattern when no valid signal is applied to RXP/RXN. This can
only be found when catching the actual rocketio recived signal. Attaching
ChipScope makes that all visible, you see the problem and you can write ip
cores that take care of that, or if you want can write simulation models
that the real behavior into account.

So I would say my statement says, if you are doing serias FPGA verification
for a longer period of time, involving projects with latest technologies
(both FPGA and outside components and circuitry) then the "on-chip"
instrumentation use is a MUST, this is what I said. Sure there are many very
serious project that can be completed very succesfully without ever using
OCI.

As of CS vs SignalTap vs Identify - all are good tools, but I wish there
would be something better. Something that is cross platform and more open in
design - ChipScope doesnt not provide option for low clock or clock enable,
or and well my wishlist is long. So long it might be easier todo by itself
then attempting to use existing tools.

Antti

that's what i thought ...

"Antti Lukats" <antti@case2000.com> wrote in message
news:cmdudc$jkf$03$1@news.t-online.com...
> "Yttrium" <Yttrium@pandora.be> wrote in message
> news:wRuid.11510$Hh1.459812@phobos.telenet-ops.be...
> > I'm experimenting with chipscope pro to test it and see if we can use it
> in
> > our company, so i got the 6.3i demo and am inserting the ILA/ICON and
VIO
> > and in the  PAR report i get:
> >
> > WARNING:Place -
> >    The structured logic associated with a shift register could not be
> placed
> > in
>
> just dont pay attention to that, it always gives zillion of similar
> warnings!
>
> advice: if you do any serious FPGA verification (with Xilinx silicon) you
> *MUST* use ChipScope - no way around it. There are other OCI solutions
> availabe of course also, but I would defenetly consider ChipScope as
primary
> tool.
>
> Antti
>
> PS I am using ChipScope to to capture at 3GS/S :)
> with rocketIO and custom "analyzer" application, kinda nice to see 3GS/S
> Logic analyzer - my primary use was capturing USB HS raw data, V2Pro
> rocketio can be directly coupled to USB (receive only)...
>
>

> As of CS vs SignalTap vs Identify - all are good tools, but I wish
there
> would be something better. Something that is cross platform and more
open in
> design - ChipScope doesnt not provide option for low clock or clock
enable,
> or and well my wishlist is long. So long it might be easier todo by
itself
> then attempting to use existing tools.
>
> Antti

Did you check out DiaLite from Temento Systems (www.temento.com)?
/daniel