Timing Issues in Quartus design

I'm facing some timing problems and I'm not really sure how to
proceed.

In this design, there is a Nios processor, and a good bit of
supporting components to interface with an external DSP (close to
9,000 LEs total).  There are two UART/fifo components (written
in-house) to support communication between the DSP and some other
components.  There were no problems until I added a third UART -- now
there are lots of timing problems.  The timing report indicates slack
times up to 30ns (on a clock that is 60Mhz).  The weird part is that
after I deleted the additional component the timing problems still
remain.  I even reverted back to the previous version from CVS, but
the timing problems still remain (and I know the version checked into
the CVS server had no timing problems two days ago).

What are the best steps to take to iron out timing problems?  Is it
worth doing some floorplanning?  or is there maybe something more
obvious that I'm overlooking?

thnx,
-P

If you have backannotated your placement assignments to labs, I would 
recommend removing them along with any Logic Lock regions that you may hae 
created and recompiliing the design. Also make sure that you have provided 
proper timing constraints for the critical paths in your design. You should 
try floorplanning only after you have completed the above two steps and your 
logic is frozen.

- Subroto Datta
Altera Corp.

"pjjones" <hjones1380@hotmail.com> wrote in message 
news:2e1d5e40.0411101135.71d53862@posting.google.com...
> I'm facing some timing problems and I'm not really sure how to
> proceed.
>
> In this design, there is a Nios processor, and a good bit of
> supporting components to interface with an external DSP (close to
> 9,000 LEs total).  There are two UART/fifo components (written
> in-house) to support communication between the DSP and some other
> components.  There were no problems until I added a third UART -- now
> there are lots of timing problems.  The timing report indicates slack
> times up to 30ns (on a clock that is 60Mhz).  The weird part is that
> after I deleted the additional component the timing problems still
> remain.  I even reverted back to the previous version from CVS, but
> the timing problems still remain (and I know the version checked into
> the CVS server had no timing problems two days ago).
>
> What are the best steps to take to iron out timing problems?  Is it
> worth doing some floorplanning?  or is there maybe something more
> obvious that I'm overlooking?
>
> thnx,
> -P