Xilinx and Altera -- maximum total bitrate for high-speed serial I/O

I'm looking ahead to an application in the future which will need a
lot of DSP power but more importantly a huge amount of I/O bandwidth
(interfacing to multiple ultra-high-speed DAC/ADCs). Up to now we've
used parallel LVDS buses at up to 1Gs/s for this, but this eats lots
of pins and is a PCB nightmare, so we plan to switch to serial I/O for
which we have on-chip transceivers available.

I've been trying to work out what total serial I/O capability is
available on the latest (and near future!) FPGAs, but it's not always
easy. In the timescales I'm looking at I guess that the likely
candidates are Virtex-4 (for which little information is available on
the MGTs), and whatever the "next-generation" Altera device is
(Stratix-II doesn't have serial I/O, Stratix GX does but may be
lacking in processing power) -- can anyone at Altera give any clue
about this?

For Virtex-4 I'm confused about what the actual serial data rate on
each pin pair is for the MGT -- I understand that there are up to 20
MGT, and that these can be "up to 12GB/s", but I assume that this is
done by bonding together 4 physical 3Gb/s channels into 1 virtual
12Gb/s channel -- is this correct?

In that case each block of 4 MGTs can do 12Gb/s; if not then this is
the rate for each MGT, but I think this is extremely unlikely -- 300ps
bit period is OK since it needs rise/fall times of about 80ps which is
achievable in this technology, but  80ps bit period needs 20ps tr/tf
which is not!

So it seems that both Altera and Xilinx are similar here; both use
blocks of 4 transceivers at 3.125/3.25Gb/s per channel, or 12.5/13Gb/s
per block. Both have a maximum of 5 blocks (20 channels) per chip.

Is this correct?

What's coming in the next couple of years as far as serial I/O is
concerned?

Cheers

Ian Dedic
Chief Engineer
Mixed Signal Division
Fujitsu Microelectronics Europe

P.S. If there are things which can only be revealed under NDA, please
contact me off-list since we have NDAs with both Xilinx and Altera.

Ian,

MGTs for V4 are 622 Mb/s to 10 Gb/s each.  They are similar to the 
already shipped and working 10 Gb/s transcievers in Virtex II Pro-X.

They can be channel bonded together for even higher aggregate data rates.

Austin

Ian Dedic wrote:

> I'm looking ahead to an application in the future which will need a
> lot of DSP power but more importantly a huge amount of I/O bandwidth
> (interfacing to multiple ultra-high-speed DAC/ADCs). Up to now we've
> used parallel LVDS buses at up to 1Gs/s for this, but this eats lots
> of pins and is a PCB nightmare, so we plan to switch to serial I/O for
> which we have on-chip transceivers available.
> 
> I've been trying to work out what total serial I/O capability is
> available on the latest (and near future!) FPGAs, but it's not always
> easy. In the timescales I'm looking at I guess that the likely
> candidates are Virtex-4 (for which little information is available on
> the MGTs), and whatever the "next-generation" Altera device is
> (Stratix-II doesn't have serial I/O, Stratix GX does but may be
> lacking in processing power) -- can anyone at Altera give any clue
> about this?
> 
> For Virtex-4 I'm confused about what the actual serial data rate on
> each pin pair is for the MGT -- I understand that there are up to 20
> MGT, and that these can be "up to 12GB/s", but I assume that this is
> done by bonding together 4 physical 3Gb/s channels into 1 virtual
> 12Gb/s channel -- is this correct?
> 
> In that case each block of 4 MGTs can do 12Gb/s; if not then this is
> the rate for each MGT, but I think this is extremely unlikely -- 300ps
> bit period is OK since it needs rise/fall times of about 80ps which is
> achievable in this technology, but  80ps bit period needs 20ps tr/tf
> which is not!
> 
> So it seems that both Altera and Xilinx are similar here; both use
> blocks of 4 transceivers at 3.125/3.25Gb/s per channel, or 12.5/13Gb/s
> per block. Both have a maximum of 5 blocks (20 channels) per chip.
> 
> Is this correct?
> 
> What's coming in the next couple of years as far as serial I/O is
> concerned?
> 
> Cheers
> 
> Ian Dedic
> Chief Engineer
> Mixed Signal Division
> Fujitsu Microelectronics Europe
> 
> P.S. If there are things which can only be revealed under NDA, please
> contact me off-list since we have NDAs with both Xilinx and Altera.

Hi Austin

Thanks for that -- I wasn't really sure that the Pro-X and V4 were
10Gb/s per channel (pair of differential pins), since people ofter
talk about "10Gb serial I/O" when they actually mean 4 bonded 2.5Gb/s
channels (or 3.2Gb/s allowing for 10B/8B encoding).

Of course 10Gb/s real data rate gets you into a whole new raft of
issues with PCB/connectors/sockets because the edge rates are so fast
-- we've done boards with a small number of 10Gb/s channels where we
had to take extreme care over things like via stubs and choice of
layers. Maybe the best compromise here is 5-6Gb/s per channel, which
would give half the number of channels compared to 2.5-3Gb/s, but be
less critical physically than 10-12Gb/s.

Cheers

Ian

P.S. Anybody else out there have any enlightening comments on this?

Austin Lesea <austin@xilinx.com> wrote in message news:<cn0ebs$ruh2@cliff.xsj.xilinx.com>...
> Ian,
> 
> MGTs for V4 are 622 Mb/s to 10 Gb/s each.  They are similar to the 
> already shipped and working 10 Gb/s transcievers in Virtex II Pro-X.
> 
> They can be channel bonded together for even higher aggregate data rates.
> 
> Austin
> 
> Ian Dedic wrote:
> 
> > I'm looking ahead to an application in the future which will need a
> > lot of DSP power but more importantly a huge amount of I/O bandwidth
> > (interfacing to multiple ultra-high-speed DAC/ADCs). Up to now we've
> > used parallel LVDS buses at up to 1Gs/s for this, but this eats lots
> > of pins and is a PCB nightmare, so we plan to switch to serial I/O for
> > which we have on-chip transceivers available.
> > 
> > I've been trying to work out what total serial I/O capability is
> > available on the latest (and near future!) FPGAs, but it's not always
> > easy. In the timescales I'm looking at I guess that the likely
> > candidates are Virtex-4 (for which little information is available on
> > the MGTs), and whatever the "next-generation" Altera device is
> > (Stratix-II doesn't have serial I/O, Stratix GX does but may be
> > lacking in processing power) -- can anyone at Altera give any clue
> > about this?
> > 
> > For Virtex-4 I'm confused about what the actual serial data rate on
> > each pin pair is for the MGT -- I understand that there are up to 20
> > MGT, and that these can be "up to 12GB/s", but I assume that this is
> > done by bonding together 4 physical 3Gb/s channels into 1 virtual
> > 12Gb/s channel -- is this correct?
> > 
> > In that case each block of 4 MGTs can do 12Gb/s; if not then this is
> > the rate for each MGT, but I think this is extremely unlikely -- 300ps
> > bit period is OK since it needs rise/fall times of about 80ps which is
> > achievable in this technology, but  80ps bit period needs 20ps tr/tf
> > which is not!
> > 
> > So it seems that both Altera and Xilinx are similar here; both use
> > blocks of 4 transceivers at 3.125/3.25Gb/s per channel, or 12.5/13Gb/s
> > per block. Both have a maximum of 5 blocks (20 channels) per chip.
> > 
> > Is this correct?
> > 
> > What's coming in the next couple of years as far as serial I/O is
> > concerned?
> > 
> > Cheers
> > 
> > Ian Dedic
> > Chief Engineer
> > Mixed Signal Division
> > Fujitsu Microelectronics Europe
> > 
> > P.S. If there are things which can only be revealed under NDA, please
> > contact me off-list since we have NDAs with both Xilinx and Altera.

Ian,

Well, I certainly understand that a speed bump to a 6 Gbs is more like a 
roadblock to a 10 Gbs signal.  Until everything catches up (pcb 
technology, SI engineering) not going for 10 Gbs if you don't have to is 
probably a good idea.  6.25 Gbs is looking quite nice, as you say, given 
  pcb and connector technologies.

And, yes, I am aware that most people mean 4 X 3.125 Gbs (using 8b10b) 
which yields an actual total aggregate bit rate of 10 Gbs when you say 
"10 Gbs channel."

Remember to divide by the coding scheme overhead to get the actual 
useful bit rate. (so even 10 Gbs using 8b/10b is less than 10 Gbs of 
useful data -- even though the bits do fly by at that 10 Gbs rate)

There is another coding scheme that is used at the higher rates, 64b66b, 
which is much more efficient (more useful bits than 8b10b).  We support 
this coding scheme, too.

Austin


Ian Dedic wrote:
> Hi Austin
> 
> Thanks for that -- I wasn't really sure that the Pro-X and V4 were
> 10Gb/s per channel (pair of differential pins), since people ofter
> talk about "10Gb serial I/O" when they actually mean 4 bonded 2.5Gb/s
> channels (or 3.2Gb/s allowing for 10B/8B encoding).
> 
> Of course 10Gb/s real data rate gets you into a whole new raft of
> issues with PCB/connectors/sockets because the edge rates are so fast
> -- we've done boards with a small number of 10Gb/s channels where we
> had to take extreme care over things like via stubs and choice of
> layers. Maybe the best compromise here is 5-6Gb/s per channel, which
> would give half the number of channels compared to 2.5-3Gb/s, but be
> less critical physically than 10-12Gb/s.
> 
> Cheers
> 
> Ian
> 
> P.S. Anybody else out there have any enlightening comments on this?
> 
> Austin Lesea <austin@xilinx.com> wrote in message news:<cn0ebs$ruh2@cliff.xsj.xilinx.com>...
> 
>>Ian,
>>
>>MGTs for V4 are 622 Mb/s to 10 Gb/s each.  They are similar to the 
>>already shipped and working 10 Gb/s transcievers in Virtex II Pro-X.
>>
>>They can be channel bonded together for even higher aggregate data rates.
>>
>>Austin
>>
>>Ian Dedic wrote:
>>
>>
>>>I'm looking ahead to an application in the future which will need a
>>>lot of DSP power but more importantly a huge amount of I/O bandwidth
>>>(interfacing to multiple ultra-high-speed DAC/ADCs). Up to now we've
>>>used parallel LVDS buses at up to 1Gs/s for this, but this eats lots
>>>of pins and is a PCB nightmare, so we plan to switch to serial I/O for
>>>which we have on-chip transceivers available.
>>>
>>>I've been trying to work out what total serial I/O capability is
>>>available on the latest (and near future!) FPGAs, but it's not always
>>>easy. In the timescales I'm looking at I guess that the likely
>>>candidates are Virtex-4 (for which little information is available on
>>>the MGTs), and whatever the "next-generation" Altera device is
>>>(Stratix-II doesn't have serial I/O, Stratix GX does but may be
>>>lacking in processing power) -- can anyone at Altera give any clue
>>>about this?
>>>
>>>For Virtex-4 I'm confused about what the actual serial data rate on
>>>each pin pair is for the MGT -- I understand that there are up to 20
>>>MGT, and that these can be "up to 12GB/s", but I assume that this is
>>>done by bonding together 4 physical 3Gb/s channels into 1 virtual
>>>12Gb/s channel -- is this correct?
>>>
>>>In that case each block of 4 MGTs can do 12Gb/s; if not then this is
>>>the rate for each MGT, but I think this is extremely unlikely -- 300ps
>>>bit period is OK since it needs rise/fall times of about 80ps which is
>>>achievable in this technology, but  80ps bit period needs 20ps tr/tf
>>>which is not!
>>>
>>>So it seems that both Altera and Xilinx are similar here; both use
>>>blocks of 4 transceivers at 3.125/3.25Gb/s per channel, or 12.5/13Gb/s
>>>per block. Both have a maximum of 5 blocks (20 channels) per chip.
>>>
>>>Is this correct?
>>>
>>>What's coming in the next couple of years as far as serial I/O is
>>>concerned?
>>>
>>>Cheers
>>>
>>>Ian Dedic
>>>Chief Engineer
>>>Mixed Signal Division
>>>Fujitsu Microelectronics Europe
>>>
>>>P.S. If there are things which can only be revealed under NDA, please
>>>contact me off-list since we have NDAs with both Xilinx and Altera.

Ian,
Stratix II GX will elevate LE count, increase transceiver speed, and
increase channel count. I think the majority of chip-to-chip and
backplane requirements in the next generation will be better addressed
by transceiver speeds in the 5-6 Gbps range than in the 10-12 Gbps
range based on supporting infrastructure required. More details on
Stratix II GX are available today with an NDA.

Dave Greenfield
Altera Marketing
> > 
> > I've been trying to work out what total serial I/O capability is
> > available on the latest (and near future!) FPGAs, but it's not always
> > easy. In the timescales I'm looking at I guess that the likely
> > candidates are Virtex-4 (for which little information is available on
> > the MGTs), and whatever the "next-generation" Altera device is
> > (Stratix-II doesn't have serial I/O, Stratix GX does but may be
> > lacking in processing power) -- can anyone at Altera give any clue
> > about this?
> > 
> > > > 
> > Cheers
> > 
> > Ian Dedic
> > Chief Engineer
> > Mixed Signal Division
> > Fujitsu Microelectronics Europe
> > 
> > P.S. If there are things which can only be revealed under NDA, please
> > contact me off-list since we have NDAs with both Xilinx and Altera.

Thanks Dave -- it sounds like all our views agree here (see other
mails in thread) that 5-6Gb/s as a next step avoids the issues which
become difficult at 10-12Gb/s. Also given the number of channels
available (from Altera and Xilinx) this will meet our requirement (up
to about 100Gb/s total throughput).

Ian

davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0411121500.176f0fdb@posting.google.com>...
> Ian,
> Stratix II GX will elevate LE count, increase transceiver speed, and
> increase channel count. I think the majority of chip-to-chip and
> backplane requirements in the next generation will be better addressed
> by transceiver speeds in the 5-6 Gbps range than in the 10-12 Gbps
> range based on supporting infrastructure required. More details on
> Stratix II GX are available today with an NDA.
> 
> Dave Greenfield
> Altera Marketing
> > > 
> > > I've been trying to work out what total serial I/O capability is
> > > available on the latest (and near future!) FPGAs, but it's not always
> > > easy. In the timescales I'm looking at I guess that the likely
> > > candidates are Virtex-4 (for which little information is available on
> > > the MGTs), and whatever the "next-generation" Altera device is
> > > (Stratix-II doesn't have serial I/O, Stratix GX does but may be
> > > lacking in processing power) -- can anyone at Altera give any clue
> > > about this?
> > > 
> > > > > 
> > > Cheers
> > > 
> > > Ian Dedic
> > > Chief Engineer
> > > Mixed Signal Division
> > > Fujitsu Microelectronics Europe
> > > 
> > > P.S. If there are things which can only be revealed under NDA, please
> > > contact me off-list since we have NDAs with both Xilinx and Altera.

Ian,

There is a definite advantage to using a transceiver designed to work at 
10 Gbs at 6.25 Gbs -- there is a lot of margin!

Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them 
has to be just perfect, and pass the production BER test.  We are in 
production.  At 10 Gbs.

And, you can see (and get delivery of) the Pro-X transceivers (today at 
the many RocketLab(tm) demo sites we have around the world).

No "will", "more details under NDA", or any of that.  Just product, 
working, on the shelf, shipping NOW.

Austin

Ian Dedic wrote:
> Thanks Dave -- it sounds like all our views agree here (see other
> mails in thread) that 5-6Gb/s as a next step avoids the issues which
> become difficult at 10-12Gb/s. Also given the number of channels
> available (from Altera and Xilinx) this will meet our requirement (up
> to about 100Gb/s total throughput).
> 
> Ian
> 
> davidg@altera.com (Dave Greenfield) wrote in message news:<5c156a0b.0411121500.176f0fdb@posting.google.com>...
> 
>>Ian,
>>Stratix II GX will elevate LE count, increase transceiver speed, and
>>increase channel count. I think the majority of chip-to-chip and
>>backplane requirements in the next generation will be better addressed
>>by transceiver speeds in the 5-6 Gbps range than in the 10-12 Gbps
>>range based on supporting infrastructure required. More details on
>>Stratix II GX are available today with an NDA.
>>
>>Dave Greenfield
>>Altera Marketing
>>
>>>>I've been trying to work out what total serial I/O capability is
>>>>available on the latest (and near future!) FPGAs, but it's not always
>>>>easy. In the timescales I'm looking at I guess that the likely
>>>>candidates are Virtex-4 (for which little information is available on
>>>>the MGTs), and whatever the "next-generation" Altera device is
>>>>(Stratix-II doesn't have serial I/O, Stratix GX does but may be
>>>>lacking in processing power) -- can anyone at Altera give any clue
>>>>about this?
>>>>
>>>>
>>>>Cheers
>>>>
>>>>Ian Dedic
>>>>Chief Engineer
>>>>Mixed Signal Division
>>>>Fujitsu Microelectronics Europe
>>>>
>>>>P.S. If there are things which can only be revealed under NDA, please
>>>>contact me off-list since we have NDAs with both Xilinx and Altera.

Hi Austin

Obviously there is more margin if you're not pushing the transceiver so 
hard, and being in the IC business I always take "real-soon-now" with a 
large pinch of salt.

But in the timescales we're looking at it seems that there will be 
solutions from both the biggest FPGA vendors, which always helps when 
talking to customers who might exclusively use one or the other...:-)

Cheers

Ian

Austin Lesea wrote:

> Ian,
> 
> There is a definite advantage to using a transceiver designed to work at 
> 10 Gbs at 6.25 Gbs -- there is a lot of margin!
> 
> Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them 
> has to be just perfect, and pass the production BER test.  We are in 
> production.  At 10 Gbs.
> 
> And, you can see (and get delivery of) the Pro-X transceivers (today at 
> the many RocketLab(tm) demo sites we have around the world).
> 
> No "will", "more details under NDA", or any of that.  Just product, 
> working, on the shelf, shipping NOW.
> 
> Austin
> 
> Ian Dedic wrote:
> 
>> Thanks Dave -- it sounds like all our views agree here (see other
>> mails in thread) that 5-6Gb/s as a next step avoids the issues which
>> become difficult at 10-12Gb/s. Also given the number of channels
>> available (from Altera and Xilinx) this will meet our requirement (up
>> to about 100Gb/s total throughput).
>>
>> Ian

Ian,

OK.  Time is on your side if you can wait.

Austin

Ian & Hilda Dedic wrote:
> Hi Austin
> 
> Obviously there is more margin if you're not pushing the transceiver so 
> hard, and being in the IC business I always take "real-soon-now" with a 
> large pinch of salt.
> 
> But in the timescales we're looking at it seems that there will be 
> solutions from both the biggest FPGA vendors, which always helps when 
> talking to customers who might exclusively use one or the other...:-)
> 
> Cheers
> 
> Ian
> 
> Austin Lesea wrote:
> 
>> Ian,
>>
>> There is a definite advantage to using a transceiver designed to work 
>> at 10 Gbs at 6.25 Gbs -- there is a lot of margin!
>>
>> Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them 
>> has to be just perfect, and pass the production BER test.  We are in 
>> production.  At 10 Gbs.
>>
>> And, you can see (and get delivery of) the Pro-X transceivers (today 
>> at the many RocketLab(tm) demo sites we have around the world).
>>
>> No "will", "more details under NDA", or any of that.  Just product, 
>> working, on the shelf, shipping NOW.
>>
>> Austin
>>
>> Ian Dedic wrote:
>>
>>> Thanks Dave -- it sounds like all our views agree here (see other
>>> mails in thread) that 5-6Gb/s as a next step avoids the issues which
>>> become difficult at 10-12Gb/s. Also given the number of channels
>>> available (from Altera and Xilinx) this will meet our requirement (up
>>> to about 100Gb/s total throughput).
>>>
>>> Ian

I would not even consider using a high-speed I/O part unless I see it
working for real on a board. And with some characterization data to
back it up. That's because engineers have been burned too many times
for claims of serial I/O greatness only to be left without working
silicon when it comes times for the rubber to hit the road.

Who cares about seeing info under NDA? 6.25 Gbps and above I/O is too
critical to count on some powerpoint presentation that claims great
I/O performance.

You can get a Xilinx V2 Pro X today and verify for yourself if it
meets your needs in the lab. Real silicon operating at 10 Gbps on a
real board. Case closed with no decision for me unless I can see a
Stratix II running on a real board.

With Xilinx you don't even need to have all the great equipment
yourself. You can go to a rocket lab and see for yourself.

Also, I would much prefer to run a 10 Gbps device at 6.25 than a 6.25
Gbps device at 6.25 Gbps. I'll take all the extra margin any day.


Ian & Hilda Dedic <news.nospam@dedics.co.uk> wrote in message news:<3099tbF2te2tsU1@uni-berlin.de>...
> Hi Austin
> 
> Obviously there is more margin if you're not pushing the transceiver so 
> hard, and being in the IC business I always take "real-soon-now" with a 
> large pinch of salt.
> 
> But in the timescales we're looking at it seems that there will be 
> solutions from both the biggest FPGA vendors, which always helps when 
> talking to customers who might exclusively use one or the other...:-)
> 
> Cheers
> 
> Ian
> 
> Austin Lesea wrote:
> 
> > Ian,
> > 
> > There is a definite advantage to using a transceiver designed to work at 
> > 10 Gbs at 6.25 Gbs -- there is a lot of margin!
> > 
> > Using a 6.25 Gbs transceiver at 6.25 Gbs means that every one of them 
> > has to be just perfect, and pass the production BER test.  We are in 
> > production.  At 10 Gbs.
> > 
> > And, you can see (and get delivery of) the Pro-X transceivers (today at 
> > the many RocketLab(tm) demo sites we have around the world).
> > 
> > No "will", "more details under NDA", or any of that.  Just product, 
> > working, on the shelf, shipping NOW.
> > 
> > Austin
> > 
> > Ian Dedic wrote:
> > 
> >> Thanks Dave -- it sounds like all our views agree here (see other
> >> mails in thread) that 5-6Gb/s as a next step avoids the issues which
> >> become difficult at 10-12Gb/s. Also given the number of channels
> >> available (from Altera and Xilinx) this will meet our requirement (up
> >> to about 100Gb/s total throughput).
> >>
> >> Ian