Digital LP filter in multiplier free FPGA

Hi All,

I need to implement a low pass digital filter on 12 bit ADC data in a Spatan
IIE device, but I'd like it to be multiplier free - in other words just use
adders and bit shifting for the coefficients. The sample rate is 12Mhz and I
need a sharp cut-off at around 3MHz. Does anyone know of a simple design
(IIR?) to do this, or a website/tutorial to give me some pointers? I've seen
several websites with coefficient calculators, there are always a few
coefficients that can't be easily calculated with bit shifting and adding.

Thanks!

Mark.

"markp" <map.nospam@f2s.com> wrote in message
news:2vn75sF2o7m4kU1@uni-berlin.de...
> Hi All,
>
> I need to implement a low pass digital filter on 12 bit ADC data in a
Spatan
> IIE device, but I'd like it to be multiplier free - in other words just
use
> adders and bit shifting for the coefficients. The sample rate is 12Mhz and
I
> need a sharp cut-off at around 3MHz. Does anyone know of a simple design
> (IIR?) to do this, or a website/tutorial to give me some pointers? I've
seen
> several websites with coefficient calculators, there are always a few
> coefficients that can't be easily calculated with bit shifting and adding.
>
> Thanks!

depending what you need, one solution is very simple "digital integrator"
its doable with only shift and add, there is some appnote or something at
xilinx web, I used that in digital carrier frequency amplifier, and it did
give actually very good filtering (for my application at least).

an example digital integrator source is appended
---------
--
-- 18 Bit Digital Integrator Feedback "multiplier"
-- constant 1 / 256 (fixed, no choices implemented)
-- Tested and working.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;

entity integrator_18bit is Port (
           rst : in std_logic;
           clk : in std_logic;
           din : in std_logic_vector(17 downto 0); -- Input: 18 Bit Unsigned
INTEGER
           k : in std_logic_vector(3 downto 0); -- multiplier select (not
implemented)
           dout : out std_logic_vector(17 downto 0) -- Output: 18 Bit
Unsigned INTEGER
           );
end integrator_18bit;

architecture Behavioral of integrator_18bit is

signal acc : std_logic_vector(25 downto 0);
signal vi_minus_vo : std_logic_vector(25 downto 0);
signal vi_minus_vo_sign_extended : std_logic_vector(7 downto 0);

begin
  -- Microblaze "endian" conversion
  dout(0) <= acc(25);  dout(1) <= acc(24);  dout(2) <= acc(23);  dout(3) <=
acc(22);
  dout(4) <= acc(21);  dout(5) <= acc(20);  dout(6) <= acc(19);  dout(7) <=
acc(18);
  dout(8) <= acc(17);  dout(9) <= acc(16);  dout(10) <= acc(15);  dout(11)
<= acc(14);
  dout(12) <= acc(13);  dout(13) <= acc(12);  dout(14) <= acc(11);  dout(15)
<= acc(10);
  dout(16) <= acc(9);  dout(17) <= acc(8);

  -- Error Value
  vi_minus_vo <= (din & "00000000") - acc;
  -- Sign Extension for Error Value
  with vi_minus_vo(25) select vi_minus_vo_sign_extended(7 downto 0) <=
"00000000" when '0', "11111111" when others;

  process (clk) begin
    if (rst='1') then
      acc <= "00000000000000000000000000";
    else
      if (clk'event and clk='1') then
        -- Accumulate
        acc <= acc + (vi_minus_vo_sign_extended(7 downto 0) & vi_minus_vo(25
downto 8));
      end if;
    end if;
  end process;

end Behavioral;

On Sat, 13 Nov 2004 19:55:43 -0000, "markp" <map.nospam@f2s.com>
wrote:

>Hi All,
>
>I need to implement a low pass digital filter on 12 bit ADC data in a Spatan
>IIE device, but I'd like it to be multiplier free - in other words just use
>adders and bit shifting for the coefficients. The sample rate is 12Mhz and I
>need a sharp cut-off at around 3MHz. Does anyone know of a simple design
>(IIR?) to do this, or a website/tutorial to give me some pointers? I've seen
>several websites with coefficient calculators, there are always a few
>coefficients that can't be easily calculated with bit shifting and adding.
>
>Thanks!
>
>Mark.
>

See zipfile in abse. If I post it here, the formatting gets lunched.

John

"John Larkin" <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in
message news:g0ucp0l3v5pmv3a8afvlil3g7b1k7u2jc1@4ax.com...
> On Sat, 13 Nov 2004 19:55:43 -0000, "markp" <map.nospam@f2s.com>
> wrote:
>
> >Hi All,
> >
> >I need to implement a low pass digital filter on 12 bit ADC data in a
Spatan
> >IIE device, but I'd like it to be multiplier free - in other words just
use
> >adders and bit shifting for the coefficients. The sample rate is 12Mhz
and I
> >need a sharp cut-off at around 3MHz. Does anyone know of a simple design
> >(IIR?) to do this, or a website/tutorial to give me some pointers? I've
seen
> >several websites with coefficient calculators, there are always a few
> >coefficients that can't be easily calculated with bit shifting and
adding.
> >
> >Thanks!
> >
> >Mark.
> >
>
> See zipfile in abse. If I post it here, the formatting gets lunched.

Thanks John. Unfortunately I've got text only news server access, any chance
in emailing? (remove .nospam).

Cheers,

Mark.
> John
>

On Sat, 13 Nov 2004 21:19:25 -0000, "markp" <map.nospam@f2s.com>
wrote:

>
>"John Larkin" <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in
>message news:g0ucp0l3v5pmv3a8afvlil3g7b1k7u2jc1@4ax.com...
>> On Sat, 13 Nov 2004 19:55:43 -0000, "markp" <map.nospam@f2s.com>
>> wrote:
>>
>> >Hi All,
>> >
>> >I need to implement a low pass digital filter on 12 bit ADC data in a
>Spatan
>> >IIE device, but I'd like it to be multiplier free - in other words just
>use
>> >adders and bit shifting for the coefficients. The sample rate is 12Mhz
>and I
>> >need a sharp cut-off at around 3MHz. Does anyone know of a simple design
>> >(IIR?) to do this, or a website/tutorial to give me some pointers? I've
>seen
>> >several websites with coefficient calculators, there are always a few
>> >coefficients that can't be easily calculated with bit shifting and
>adding.
>> >
>> >Thanks!
>> >
>> >Mark.
>> >
>>
>> See zipfile in abse. If I post it here, the formatting gets lunched.
>
>Thanks John. Unfortunately I've got text only news server access, any chance
>in emailing? (remove .nospam).
>
>Cheers,
>
>Mark.
>> John
>>
>


OK, done, I think.

John

On Sat, 13 Nov 2004 13:10:15 -0800, John Larkin
<jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote:

>On Sat, 13 Nov 2004 19:55:43 -0000, "markp" <map.nospam@f2s.com>
>wrote:
>
>>Hi All,
>>
>>I need to implement a low pass digital filter on 12 bit ADC data in a Spatan
>>IIE device, but I'd like it to be multiplier free - in other words just use
>>adders and bit shifting for the coefficients. The sample rate is 12Mhz and I
>>need a sharp cut-off at around 3MHz. Does anyone know of a simple design
>>(IIR?) to do this, or a website/tutorial to give me some pointers? I've seen
>>several websites with coefficient calculators, there are always a few
>>coefficients that can't be easily calculated with bit shifting and adding.
>>
>>Thanks!
>>
>>Mark.
>>
>
>See zipfile in abse. If I post it here, the formatting gets lunched.
>
>John


Oops, K1 should be 4, 1/16. File got scrambled somehow.

John

> I need to implement a low pass digital filter on 12 bit ADC data in a 
> Spatan
> IIE device, but I'd like it to be multiplier free - in other words just 
> use
> adders and bit shifting for the coefficients. The sample rate is 12Mhz and 
> I
> need a sharp cut-off at around 3MHz. Does anyone know of a simple design
> (IIR?) to do this, or a website/tutorial to give me some pointers? I've 
> seen
> several websites with coefficient calculators, there are always a few
> coefficients that can't be easily calculated with bit shifting and adding.

Hi Mark,

I can help you out with this by automatically generating VHDL for an FIR 
implementation for your filter that uses shifts and adds.

Please post the following details:


Do you want the filter to run at 12MHz (i.e. full-parallel) or do you have a 
faster clock available that could be used to share hardware over multiple 
clock cycles?

Is the filter single-rate or are you decimating?

Input bit-width?

Signed/unsigned input?

Quantised filter coefficients (integers ideally but fixed-point will do) or 
more detailed spectral requirements (what -dB gain at 3MHz, pass-band ripple 
etc., start rolling off at what freq, stop rolling of at what freq. etc.)


Cheers,

Ken

"markp" <map.nospam@f2s.com> wrote in message news:<2vn75sF2o7m4kU1@uni-berlin.de>...
> Hi All,
> 
> I need to implement a low pass digital filter on 12 bit ADC data in a Spatan
> IIE device, but I'd like it to be multiplier free - in other words just use
> adders and bit shifting for the coefficients. The sample rate is 12Mhz and I
> need a sharp cut-off at around 3MHz. Does anyone know of a simple design
> (IIR?) to do this, or a website/tutorial to give me some pointers? I've seen
> several websites with coefficient calculators, there are always a few
> coefficients that can't be easily calculated with bit shifting and adding.
> 
> Thanks!
> 
> Mark.

You didn't say how sharp your cutoff needs to be, or how much gain
ripple you can tolerate. You might consider a pipelined multiplier
design. This will result in very high clock rates, permitting one
multiplier to handle 8-16 coefficients. Several multipliers can be
used in parallel to increase the number of coefficients even further.
Xilinx has numerous ap notes on digital filtering techniques. Here is
a good review of the topic:
http://www.andraka.com/multipli.htm
This is probably the best book on the subject:
http://www.amazon.com/exec/obidos/ASIN/3540413413/andraka/103-1626470-7551837

Tom

<snip>
>
> OK, done, I think.
>
> John

Thanks John. I'm not really sure how to tweek this for my system, but very
interesting stuff nonetheless. I decided in the end to go for a 'rolling
average' type filter (rectangular) with 16 taps, and this seems to be
working quite nicely so I think I'll stick with this.

Regards,

Mark.

"Ken" <aeu96186@NOSPAM.yahoo.co.uk> wrote in message
news:cn69m5$rme$05$1@news.t-online.com...
> > I need to implement a low pass digital filter on 12 bit ADC data in a
> > Spatan
> > IIE device, but I'd like it to be multiplier free - in other words just
> > use
> > adders and bit shifting for the coefficients. The sample rate is 12Mhz
and
> > I
> > need a sharp cut-off at around 3MHz. Does anyone know of a simple design
> > (IIR?) to do this, or a website/tutorial to give me some pointers? I've
> > seen
> > several websites with coefficient calculators, there are always a few
> > coefficients that can't be easily calculated with bit shifting and
adding.
>
> Hi Mark,
>
> I can help you out with this by automatically generating VHDL for an FIR
> implementation for your filter that uses shifts and adds.
>
> Please post the following details:
>
>
> Do you want the filter to run at 12MHz (i.e. full-parallel) or do you have
a
> faster clock available that could be used to share hardware over multiple
> clock cycles?
>
> Is the filter single-rate or are you decimating?
>
> Input bit-width?
>
> Signed/unsigned input?
>
> Quantised filter coefficients (integers ideally but fixed-point will do)
or
> more detailed spectral requirements (what -dB gain at 3MHz, pass-band
ripple
> etc., start rolling off at what freq, stop rolling of at what freq. etc.)
>
>
> Cheers,
>
> Ken


Hi Ken,

Well I've gone for a rolling average filter at the moment, but the specs
are:

 > Do you want the filter to run at 12MHz (i.e. full-parallel) or do you
> have a  faster clock available that could be used to share hardware
> over multiple clock cycles?

I've got a 65MHz clock and currently dividing by 6 to give 13MHz.

> Is the filter single-rate or are you decimating?

Single rate so far.

> Input bit-width?

12 bit ADC data.

> Signed/unsigned input?

Unsigned.

> Quantised filter coefficients (integers ideally but fixed-point will
> do) or more detailed spectral requirements (what -dB gain at
> 3MHz, pass-band ripple etc., start rolling off at what freq, stop
> rolling of at what freq. etc.)

-3db @ 3MHz, 4th order Butterworth type roll-off ideally, unity gain
otherwise.

Thanks!

Mark.