dual-write port BRAM with XST/Webpack

Hi I was wondering if anyone here can help me. 

I need to infer a true dual port BRAM with seperate clk, addr, data,
en and wr lines on a Spartan-3 device but according to the XST manual
this is not supported and after googling for a couple of days I've
come to a dead end.

I need this in order to provide an external memory interface to some
shared memory and the design is so simple and clean at the moment that
I really want avoid having to use an async FIFO which would need alot
of re-jigging to the upper levels and make things quite ugly.

Does anyone know if this is even possible with the free ISE Webpack
tools? Or will it require me buying some other software?  This is my
first FPGA design and is more of a hobby that may have some commercial
potential so I cant really justify spending lots of $$$ for something
I may only require the use of once.

Many thanks in advance.

Kotek Barajazz <darkgold@lycos.co.uk> wrote:

> I need to infer a true dual port BRAM with seperate clk, addr, data,
> en and wr lines on a Spartan-3 device but according to the XST manual
> this is not supported and after googling for a couple of days I've
> come to a dead end.
>
> I need this in order to provide an external memory interface to some
> shared memory and the design is so simple and clean at the moment that
> I really want avoid having to use an async FIFO which would need alot
> of re-jigging to the upper levels and make things quite ugly.
>
> Does anyone know if this is even possible with the free ISE Webpack
> tools? Or will it require me buying some other software?  This is my
> first FPGA design and is more of a hobby that may have some commercial
> potential so I cant really justify spending lots of $$$ for something
> I may only require the use of once.

You cannot infer dual-port BRAM with Webpack, but you can instantiate
primitives.  See
http://groups.google.dk/groups?hl=en&lr=&selm=vGhO5.241%24ey5.18887%40news000.worldonline.dk

Karl Olsen

Kotek Barajazz wrote:

> I need to infer a true dual port BRAM with seperate clk, addr, data,
> en and wr lines on a Spartan-3 device but according to the XST manual
> this is not supported and after googling for a couple of days I've
> come to a dead end.
> 
> I need this in order to provide an external memory interface to some
> shared memory and the design is so simple and clean at the moment that
> I really want avoid having to use an async FIFO which would need alot
> of re-jigging to the upper levels and make things quite ugly.

A fifo-like controller requires one read-only port
and one write-only port. Such a two port description
infers the "true dual port BRAM" just fine,
but with the extra read and write controls tied off.
As an added benefit, the description is portable
across vendors. Related posting:

http://groups.google.com/groups?q=infer+RAM_B4_S16_S16

      -- Mike Treseler

darkgold@lycos.co.uk (Kotek Barajazz) wrote in message news:<8196a0da.0411270742.21b443d2@posting.google.com>...
> Hi I was wondering if anyone here can help me. 
> 
> I need to infer a true dual port BRAM with seperate clk, addr, data,
> en and wr lines on a Spartan-3 device but according to the XST manual
> this is not supported and after googling for a couple of days I've
> come to a dead end.

XST can't infer it but you can instatiate the primitives instead.

have a look at: 

http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0372_356.html 
 

-Lasse

Mike Treseler wrote:
> 
> Kotek Barajazz wrote:
> 
> > I need to infer a true dual port BRAM with seperate clk, addr, data,
> > en and wr lines on a Spartan-3 device but according to the XST manual
> > this is not supported and after googling for a couple of days I've
> > come to a dead end.
> >
> > I need this in order to provide an external memory interface to some
> > shared memory and the design is so simple and clean at the moment that
> > I really want avoid having to use an async FIFO which would need alot
> > of re-jigging to the upper levels and make things quite ugly.
> 
> A fifo-like controller requires one read-only port
> and one write-only port. Such a two port description
> infers the "true dual port BRAM" just fine,
> but with the extra read and write controls tied off.
> As an added benefit, the description is portable
> across vendors. Related posting:
> 
> http://groups.google.com/groups?q=infer+RAM_B4_S16_S16

But this description only works if you have a common clock.  The OP has
asked for separate read/write clocks.  

I have never seen an example of inferrence of a dual port RAM with
separate clocks.  I can write a VHDL description of one by using a
shared variable for the RAM.  But I have not found a synthesizer that
supports shared variables.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

rickman wrote:

> But this description only works if you have a common clock.  The OP has
> asked for separate read/write clocks.  
> 
> I have never seen an example of inferrence of a dual port RAM with
> separate clocks.  

Try this one.
             -- Mike Treseler
--_________________________________


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity dual_port_ram is
    generic (
       WIDTH : integer := 32;
       DEPTH : integer := 10
       );
    port (
       w_clk     : in std_logic;
       w_en_in   : in std_logic;
       w_addr_in : in std_logic_vector(DEPTH-1 downto 0);
       w_data_in : in std_logic_vector(WIDTH-1 downto 0);

       r_clk      : in  std_logic;
       r_addr_in  : in  std_logic_vector(DEPTH-1 downto 0);
       r_data_out : out std_logic_vector(WIDTH-1 downto 0)
       );
end entity;


architecture xilinx of dual_port_ram is

    type memory_type is array (natural range <>) of
       std_logic_vector(WIDTH-1 downto 0);
    signal memory : memory_type(2**DEPTH-1 downto 0);

    signal r_addr_int : std_logic_vector(DEPTH-1 downto 0);

begin

    write : process(w_clk)
    begin
       if w_clk'event and w_clk = '1' then
          if w_en_in = '1' then
             memory(to_integer(unsigned(w_addr_in))) <= w_data_in;
          end if;
       end if;
    end process;

    read : process(r_clk)
    begin
       if r_clk'event and r_clk = '1' then
          r_addr_int <= r_addr_in;
       end if;
    end process;

    r_data_out <= memory(to_integer(unsigned(r_addr_int)));

end architecture;

Mike Treseler wrote:
> 
> rickman wrote:
> 
> > But this description only works if you have a common clock.  The OP has
> > asked for separate read/write clocks.
> >
> > I have never seen an example of inferrence of a dual port RAM with
> > separate clocks.
> 
> Try this one.
>              -- Mike Treseler
> --_________________________________
> 
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> 
> entity dual_port_ram is
>     generic (
>        WIDTH : integer := 32;
>        DEPTH : integer := 10
>        );
>     port (
>        w_clk     : in std_logic;
>        w_en_in   : in std_logic;
>        w_addr_in : in std_logic_vector(DEPTH-1 downto 0);
>        w_data_in : in std_logic_vector(WIDTH-1 downto 0);
> 
>        r_clk      : in  std_logic;
>        r_addr_in  : in  std_logic_vector(DEPTH-1 downto 0);
>        r_data_out : out std_logic_vector(WIDTH-1 downto 0)
>        );
> end entity;
> 
> architecture xilinx of dual_port_ram is
> 
>     type memory_type is array (natural range <>) of
>        std_logic_vector(WIDTH-1 downto 0);
>     signal memory : memory_type(2**DEPTH-1 downto 0);
> 
>     signal r_addr_int : std_logic_vector(DEPTH-1 downto 0);
> 
> begin
> 
>     write : process(w_clk)
>     begin
>        if w_clk'event and w_clk = '1' then
>           if w_en_in = '1' then
>              memory(to_integer(unsigned(w_addr_in))) <= w_data_in;
>           end if;
>        end if;
>     end process;
> 
>     read : process(r_clk)
>     begin
>        if r_clk'event and r_clk = '1' then
>           r_addr_int <= r_addr_in;
>        end if;
>     end process;
> 
>     r_data_out <= memory(to_integer(unsigned(r_addr_int)));
> 
> end architecture;

Ok, this is dual port, but I meant one that was fully dual port with
write on both ports.  The Xilinx dual port rams in the Virtex and later
parts (IIRC, the Spartan3 for sure) have both read and write on each
port.  Being able to write to a common RAM from two processes is not
supported in VHDL as far as I am aware.  Using a shared variable seems
to work in simulation, but is not synthesizable.  

Please correct me (further) if I am mistaken.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag
news:41A98900.4AF5BDDA@yahoo.com...

> Ok, this is dual port, but I meant one that was fully dual port with
> write on both ports.  The Xilinx dual port rams in the Virtex and later
> parts (IIRC, the Spartan3 for sure) have both read and write on each
> port.  Being able to write to a common RAM from two processes is not
> supported in VHDL as far as I am aware.  Using a shared variable seems
> to work in simulation, but is not synthesizable.

At the end, I prefer to instanciate such tings anyway. Much easier,
predictable, portable.
Why bother with semi-intelligent synthesis tools?

Regards
Falk

rickman wrote:

> Ok, this is dual port, but I meant one that was fully dual port with
> write on both ports. 

My point was that a pseudo dual port is all you
need for a fifo and that a fifo-based controller
would solve the OP's problem.

"A fifo-like controller requires one read-only port
and one write-only port. Such a two port description
infers the "true dual port BRAM" just fine,
but with the extra read and write controls tied off.
As an added benefit, the description is portable
across vendors. "


> The Xilinx dual port rams in the Virtex and later
> parts (IIRC, the Spartan3 for sure) have both read and write on each
> port.

I realize that. Reread the above.

> Being able to write to a common RAM from two processes is not
> supported in VHDL as far as I am aware.  Using a shared variable seems
> to work in simulation, but is not synthesizable.  
> 
> Please correct me (further) if I am mistaken.  

You are mistaken. I tested the two-clock version
on Leonardo for Xilinx and on modelsim Maybe you could try it
on XST and post the result.

My examples do not use a shared variable, nor did I recommend one.

         -- Mike Treseler

Falk Brunner wrote:

> At the end, I prefer to instanciate such tings anyway. Much easier,
> predictable, portable.
> Why bother with semi-intelligent synthesis tools?

Sorry to waste your time.
I suppose vhdl synthesis is a little off-topic for this group.

           -- Mike Treseler