CMOS capacitive loads, transition probabilities and FPGAs

Hello folks,

I often see the following equation to define the dynamic power consumption 
of a node in a CMOS circuit:

P = aCV^2F

where:


P = dynamic power

a = ** average number of times in a clock cycle a node with capacitance C 
will make a power consuming transition **

V= supply voltage

F = clock rate


My question is related to the definition of 'a'.  In a CMOS related paper I 
have seen 'a' defined as the average number of "0 to 1" transitions in a 
clock cycle since that is when power is drawn from the supply (half being 
stored in the cap and half being dissipated in the node).  The 1 to 0 
transition does not draw power from the supply, only the power previously 
stored in the cap on the 0 to 1 transition is dissipated.

However, in some FPGA related papers, I see 'a' being defined as the 
probability of a 0 to 1 or a 1 to 0 transition during a clock cycle.

Hence my confusion...

Can anyone shed any light on why this might be (or are the FPGA papers I've 
seen just wrong)?

Many thanks for your time,

Ken

Ken,

A commont confusion is what dissipates power?

When you charge a node, you waste power in the resistance of the 
charging transistor.

When you discharge a node, you then waste power in the resistance of the 
discharging transistors (both generate heat).

If both edges generate heat, then you have to count them both.

The energy stored in a capacitor is 1/2 CV^2, but don't let that confuse 
you:  you have to put it in, and then take it out!  The devices that do 
the work dissipate the power.

Austin

Ken wrote:
> Hello folks,
> 
> I often see the following equation to define the dynamic power consumption 
> of a node in a CMOS circuit:
> 
> P = aCV^2F
> 
> where:
> 
> 
> P = dynamic power
> 
> a = ** average number of times in a clock cycle a node with capacitance C 
> will make a power consuming transition **
> 
> V= supply voltage
> 
> F = clock rate
> 
> 
> My question is related to the definition of 'a'.  In a CMOS related paper I 
> have seen 'a' defined as the average number of "0 to 1" transitions in a 
> clock cycle since that is when power is drawn from the supply (half being 
> stored in the cap and half being dissipated in the node).  The 1 to 0 
> transition does not draw power from the supply, only the power previously 
> stored in the cap on the 0 to 1 transition is dissipated.
> 
> However, in some FPGA related papers, I see 'a' being defined as the 
> probability of a 0 to 1 or a 1 to 0 transition during a clock cycle.
> 
> Hence my confusion...
> 
> Can anyone shed any light on why this might be (or are the FPGA papers I've 
> seen just wrong)?
> 
> Many thanks for your time,
> 
> Ken
> 
> 
> 

Ken wrote:

> Hello folks,
> 
> I often see the following equation to define the dynamic power consumption 
> of a node in a CMOS circuit:
> 
> P = aCV^2F
> 
> where:
> 
> 
> P = dynamic power
> 
> a = ** average number of times in a clock cycle a node with capacitance C 
> will make a power consuming transition **
> 
> V= supply voltage
> 
> F = clock rate
> 
> 
> My question is related to the definition of 'a'.  In a CMOS related paper I 
> have seen 'a' defined as the average number of "0 to 1" transitions in a 
> clock cycle since that is when power is drawn from the supply (half being 
> stored in the cap and half being dissipated in the node).  The 1 to 0 
> transition does not draw power from the supply, only the power previously 
> stored in the cap on the 0 to 1 transition is dissipated.
> 
> However, in some FPGA related papers, I see 'a' being defined as the 
> probability of a 0 to 1 or a 1 to 0 transition during a clock cycle.
> 
> Hence my confusion...
> 
> Can anyone shed any light on why this might be (or are the FPGA papers I've 
> seen just wrong)?

  Where logic devices quote a Power Dissapation capacitance ( most glue 
logic does ), they adjust the 'C' so you plug in F
( ie that's two edges )
  The C is thus more a modeling value, to get the Power/Freq to Fit.
  Nailing F is also not simple, as decode glitches and runt pulses can
cost power, and real power is a combinaton of Clock Tree, and D-Q loadings.
  Measure of a real operating device is always a good idea :)

-jg

Austin Lesea wrote:
> 
> Ken,
> 
> A commont confusion is what dissipates power?
> 
> When you charge a node, you waste power in the resistance of the
> charging transistor.
> 
> When you discharge a node, you then waste power in the resistance of the
> discharging transistors (both generate heat).
> 
> If both edges generate heat, then you have to count them both.
> 
> The energy stored in a capacitor is 1/2 CV^2, but don't let that confuse
> you:  you have to put it in, and then take it out!  The devices that do
> the work dissipate the power.

This is a bit misleading and irrelevant.  The fact that power is only
dissipated in the resistance has nothing to do with the total amount of
energy expended in charging and discharging a capacitor.  Regardless of
what value resistance, even if it is not constant, the energy drawn from
the supply is the same as long as the capacitor is charged to the same
voltage.  The energy may be dissipated in the transistor or in the poly
track or a metal track or the bond wire or the external pin or even in
the wire from the power supply to the board.  But add them all up and
you will get the same value each time you charge a capacitor to a given
voltage.  

So the amount of power consumed is related to the frequency of
transitions and the size of the capacitance.  Whether you calculate it
from the rate of the rising edges or both edges is not relevant, that
just changes the constant that you use by a factor of 2.  As the OP
said, when you charge the cap from 0 volts to Vcc, half goes into the
cap and half is wasted.  But the total always comes from the PSU and is
always the same amount.  

You can't have a 0 to 1 transition without a 1 to 0 transition, so why
is this even an issue?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

rickman wrote:

(snip of (1/2) C V**2 discussion)

> This is a bit misleading and irrelevant.  The fact that power is only
> dissipated in the resistance has nothing to do with the total amount of
> energy expended in charging and discharging a capacitor.  Regardless of
> what value resistance, even if it is not constant, the energy drawn from
> the supply is the same as long as the capacitor is charged to the same
> voltage.  The energy may be dissipated in the transistor or in the poly
> track or a metal track or the bond wire or the external pin or even in
> the wire from the power supply to the board.  But add them all up and
> you will get the same value each time you charge a capacitor to a given
> voltage.  

> So the amount of power consumed is related to the frequency of
> transitions and the size of the capacitance.  Whether you calculate it
> from the rate of the rising edges or both edges is not relevant, that
> just changes the constant that you use by a factor of 2.  As the OP
> said, when you charge the cap from 0 volts to Vcc, half goes into the
> cap and half is wasted.  But the total always comes from the PSU and is
> always the same amount.  

> You can't have a 0 to 1 transition without a 1 to 0 transition, so why
> is this even an issue?  

The issue is where the factor of two goes.

As previously said, when charging half is dissipated, and half goes
into the capacitor.  When discharging the rest is dissipated.

For some designs it is easier to count total transitions than to
count rising or falling transitions.  Otherwise, yes, it doesn't
matter as long as the 2 and 1/2 are in the right place.

-- glen

Hi chaps,

Many thanks for the replies.

(snip)

> For some designs it is easier to count total transitions than to
> count rising or falling transitions.  Otherwise, yes, it doesn't
> matter as long as the 2 and 1/2 are in the right place.

So, if 'a' is counting 0 to 1 only, then:

P = aCV^2F

is correct.

If 'a' is counting 0 to 1 and 1 to 0 then

P = 0.5aCV^2F

is correct.

Correct?  :-)

In the 2nd case we use 0.5 because the 1 to 0 transitions dissipate energy 
already drawn on the 0 to 1 transitions and we do not want to count it 
twice?

I have seen the 2nd equation quoted often also with 'a' being referred to as 
the transition density at the node (which I assume means 0 to 1 and 1 to 0). 
I have also seen the 1st equation quoted with the same definition for 'a'. 
They can't both use the same definition for 'a' and be right....

Cheers,

Ken

Ken wrote:
> Hi chaps,
> 
> Many thanks for the replies.
> 
> (snip)
> 
> 
>>For some designs it is easier to count total transitions than to
>>count rising or falling transitions.  Otherwise, yes, it doesn't
>>matter as long as the 2 and 1/2 are in the right place.
> 
> 
> So, if 'a' is counting 0 to 1 only, then:
> 
> P = aCV^2F
> 
> is correct.
> 
> If 'a' is counting 0 to 1 and 1 to 0 then
> 
> P = 0.5aCV^2F
> 
> is correct.
> 
> Correct?  :-)
> 
> In the 2nd case we use 0.5 because the 1 to 0 transitions dissipate energy 
> already drawn on the 0 to 1 transitions and we do not want to count it 
> twice?
> 
> I have seen the 2nd equation quoted often also with 'a' being referred to as 
> the transition density at the node (which I assume means 0 to 1 and 1 to 0). 
> I have also seen the 1st equation quoted with the same definition for 'a'. 
> They can't both use the same definition for 'a' and be right....

  They can if they adjust C :)
  If you are in a physics class, you have know C, ( and so 1 / 0/5 
matters) but inside the devices, there are many C's and many drivers, so 
you choose an _effective_ C to match a point on the Power/Freq curve.
  If you want F to be edges, or F to be Clock that's up to you.

  The above eqn gives a feel for the physics, but is not the whole story.
In data sheets, you will see a series of Power Dissipation Capacitance 
[effective] values quoted, to give the best fit for operating conditions.
   [ and of course, none of this factors in device leakage ]
-jg

Ken wrote:
(snip regarding energy dissipation in CMOS)

> So, if 'a' is counting 0 to 1 only, then:

> P = aCV^2F

> is correct.

> If 'a' is counting 0 to 1 and 1 to 0 then

> P = 0.5aCV^2F

> is correct.

> Correct?  :-)

> In the 2nd case we use 0.5 because the 1 to 0 transitions dissipate energy 
> already drawn on the 0 to 1 transitions and we do not want to count it 
> twice?

The 1/2 comes from the integral of V dV, which is 0.5*V**2, or, as you
said earlier, half ends up in the capacitor and half in the resistor.
Stored energy in a capacitor is always 0.5*C*V**2.

-- glen

glen herrmannsfeldt wrote:
> 
> rickman wrote:
> 
> (snip of (1/2) C V**2 discussion)
> 
> > This is a bit misleading and irrelevant.  The fact that power is only
> > dissipated in the resistance has nothing to do with the total amount of
> > energy expended in charging and discharging a capacitor.  Regardless of
> > what value resistance, even if it is not constant, the energy drawn from
> > the supply is the same as long as the capacitor is charged to the same
> > voltage.  The energy may be dissipated in the transistor or in the poly
> > track or a metal track or the bond wire or the external pin or even in
> > the wire from the power supply to the board.  But add them all up and
> > you will get the same value each time you charge a capacitor to a given
> > voltage.
> 
> > So the amount of power consumed is related to the frequency of
> > transitions and the size of the capacitance.  Whether you calculate it
> > from the rate of the rising edges or both edges is not relevant, that
> > just changes the constant that you use by a factor of 2.  As the OP
> > said, when you charge the cap from 0 volts to Vcc, half goes into the
> > cap and half is wasted.  But the total always comes from the PSU and is
> > always the same amount.
> 
> > You can't have a 0 to 1 transition without a 1 to 0 transition, so why
> > is this even an issue?
> 
> The issue is where the factor of two goes.
> 
> As previously said, when charging half is dissipated, and half goes
> into the capacitor.  When discharging the rest is dissipated.
> 
> For some designs it is easier to count total transitions than to
> count rising or falling transitions.  Otherwise, yes, it doesn't
> matter as long as the 2 and 1/2 are in the right place.

I don't know of any chip power calculations that require you to come up
with the constant yourself.  If the chip vendor gives you a constant and
tells you to multiply by 1/2 or multiply by 2 or to just use the
constant as is, then where is the problem?  I think the OP was just
confused about the variations in the formulae.  It is just a matter of
how you figure the constant.  Normally the constant is measured rather
than calculated, so you just need to use the formulae that you are given
with the constant.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Hi Ken et al:

Just a couple more points on power equations.  As some posters have 
indicated, the kCV^2f equations give you the right shape, and simple power 
models are tuned to make it work.  One thing that works for the developers 
of power models is what goes up must come down -- the number of 0->1 and 
1->0 transitions are equal.  So if we can get one constant that represents 
the total switching current from supply to ground for a pair of transitions, 
we can then multiply that by the frequency of transition and the supply 
voltage to come up with a good stab at dynamic power over a set of 
transitions.

It is worth noting that there are many factors that go into the current 
drawn during switching.  In addition to the charging & discharging of 
capacitance, you also have the crow-bar or short-circuit current of CMOS 
logic.  This current will depend on whether you have a rising or falling 
edge due to different rise- and fall-delays (and input slew rates) which 
depends on the exact ratioing of the logic and upstream drivers.  But again, 
if you measure the power over a rising + falling edge and average it to get 
power per transition, this will work out.

Provided the assumption that switching current is linear in activity holds, 
you can lump the short-circuit current in with the charge/discharge current. 
Really you're just making an equation P = kf -- there is no physical 
capacitance in the equation anymore.  One ramification is that such a model 
for a driver + wire cannot be scaled with wirelength to obtain a power 
estimate for a different wire -- the short circuit component does not scale 
the same way as the capacitive component.

At some point this P = kf model breaks down since rapidly switching nodes 
may not fully charge/discharge caps (or equivalently hit full rail-to-rail 
swing) since there is not enough time to do so.  So "k" values obtained at 
low switching rates will tend to be pessimistic at high frequencies -- but 
that's probably good enough.  You can make things arbitrarily complicated by 
considering crazy things like as power draw increases so too does voltage 
droop, so dynamic power per transition can actually drop...  but these 
effects are subtle and the reality is that the biggest source of power error 
is lack of good estimates of switching activity per node!

Another fun part of things is that there must be enough constants k for all 
the various resources and situations of interest.  For example, the 
switching power of a gate can depend on the logic values seen at the various 
inputs (beyond just affecting whether the gate toggles).  This 
"state-dependent" dynamic power is a detail that could be ignored by taking 
an average or representative case and hoping that no design repeatedly hits 
a corner case, or it can be modeled if it is deemed important.

As discussed in some postings, you usually do not care where power is burned 
provided it is burnt on-chip -- view the circuit as a black box and you get 
Power = Current Drawn * Voltage.  But if you take terminated I/O standards 
as an example, there is some complication since current supplied by on-chip 
rails is partially dissipated off chip.  If you are designing your power 
supply, you want to know the current.  If you are designing your cooling 
solution, you want to know the on-chip power dissipation.  If you are 
looking at your system thermal management, total power dissipation is what 
you want.

The bottom line is 1/2CV^2F just begins to scratch the surface of the 
wonderful world of power!

Regards,

Paul Leventis
Altera Corp.