altera DDR core simulation with NCSim

Quite a simple question: how to simulate the DDR-SDRAM core from Altera in 
NCSim. I just can 't figure it out though Altera *claims* to support NCSim. To 
me it looks like their development chain is realy ModelSim/Quartus only...

The things I've tried:
* simulate netlist from core (yes I've got a license) : doesnt' work due to 
errors when trying to compile the thing.
* dump a "functional description" of the core: works but I'm missing some 
important functionality like burst length settings and so on. The IP generation 
tool doesn't seem to work in Linux so it's switching back and forth to Windows 
when I want to change something in the core.

Anyone a sollution?
To Altera: lovely FPGA's but quite crapy software (did I mention how many times 
Quartus crashes in Windows?). Sorry to say that.

Jan

Hi Jan,
     We are sorry to hear that the Quartus software crashed on Windows for 
you. We are definitely interested in understanding this fully and resolving 
the matter for you. The stability of the Quartus software on all supported 
platforms is very good, based on customer feedback which we monitor very 
closely. If there are specific Internal Error messages or sequences of steps 
that causedQuartusto crash, do email them to me and I will follow up with 
you by mail.

I will send you a separate reply on the DDR core simulation and Linux 
questions.

Hope this helps.
- Subroto Datta
Altera Corp.

"Jan De Ceuster" <jandc@elis.ugent.be> wrote in message 
news:cpk2a2$6ns$1@gaudi2.UGent.be...
> Quite a simple question: how to simulate the DDR-SDRAM core from Altera in 
> NCSim. I just can 't figure it out though Altera *claims* to support 
> NCSim. To me it looks like their development chain is realy 
> ModelSim/Quartus only...
>
> The things I've tried:
> * simulate netlist from core (yes I've got a license) : doesnt' work due 
> to errors when trying to compile the thing.
> * dump a "functional description" of the core: works but I'm missing some 
> important functionality like burst length settings and so on. The IP 
> generation tool doesn't seem to work in Linux so it's switching back and 
> forth to Windows when I want to change something in the core.
>
> Anyone a sollution?
> To Altera: lovely FPGA's but quite crapy software (did I mention how many 
> times Quartus crashes in Windows?). Sorry to say that.
>
> Jan 

Jan De Ceuster wrote:

> * simulate netlist from core (yes I've got a license) : doesnt' work due 
> to errors when trying to compile the thing.

Consider posting the first few error messages.

         -- Mike Treseler

>> * simulate netlist from core (yes I've got a license) : doesnt' work 
>> due to errors when trying to compile the thing.
> 
> 
> Consider posting the first few error messages.

Yeah I know, I should give more information though no workarounds possbile 
(besides of editing the code) I think.

here it is:

ncvhdl: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
          |
ncvhdl_p: *E,NOTRUS (ddr_test.vho,16316|9): illegal trailing underline [13.3].
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
           |
ncvhdl_p: *E,MISCOL (ddr_test.vho,16316|10): expecting a colon (':') 93[4.3.1.2].
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
                                           |
ncvhdl_p: *E,NOLDUS (ddr_test.vho,16316|42): illegal leading underline [13.3].
SIGNAL ww_\g_local_buffered_if:wdata_fifo\_q : std_logic_vector(29 DOWNTO 0);

Synopsys DC gives the same error (mind that the 'arrow' points at the first 
backslash):

SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 DOWNTO 0);
           ^
**Error: /home/jandc/test/test_netlist/ddr_test.vho  line 16316
         Invalid delimiter character: `\'. (VSS-965)

I think that the _\ construction is illegal but to be honnest: I've no desire to 
dig in the vhdl reference to see who is right, Cadence and  Synopsys versus Altera.

Hi Jan,

    Use the Quartus Assignments->Settings->EDA Settings->Simulation dialog 
to set the Target simulator to NCVHDL and check the Map Illegal VHDL 
characters box. This will force the illegal characters to be mapped to legal 
characters. We are still interested in understanding how the netlist with th 
eillegal characters was generated.

Hope this helps.
- Subroto Datta
Altera Corp.

"Jan De Ceuster" <jandc@elis.ugent.be> wrote in message 
news:cpkaji$9ma$1@gaudi2.UGent.be...
>>> * simulate netlist from core (yes I've got a license) : doesnt' work due 
>>> to errors when trying to compile the thing.
>>
>>
>> Consider posting the first few error messages.
>
> Yeah I know, I should give more information though no workarounds possbile 
> (besides of editing the code) I think.
>
> here it is:
>
> ncvhdl: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
> SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 
> DOWNTO 0);
>          |
> I think that the _\ construction is illegal but to be honnest: I've no 
> desire to dig in the vhdl reference to see who is right, Cadence and 
> Synopsys versus Altera. 

Hi Subroto,

the netlist was generated in the fasted way I could get that netlist. I 
took the generated DDR SDRAM core from the Altera IP libary (version 
2.2) and putted it in a Quartus II 4.1 projectfile on a Stratix FPGA. 
I've did no pinassignments whatsoever (or any other assignment) and the 
compiled the whole thing and let Quartus dump out a NCSim (here I am 
again) VHDL netlist. So in short: generate DDR core, dump it in Quartus 
4.1 as is and compile to netlist.

Jan

> Hi Jan,
> 
>     Use the Quartus Assignments->Settings->EDA Settings->Simulation dialog 
> to set the Target simulator to NCVHDL and check the Map Illegal VHDL 
> characters box. This will force the illegal characters to be mapped to legal 
> characters. We are still interested in understanding how the netlist with th 
> eillegal characters was generated.
> 
> Hope this helps.
> - Subroto Datta
> Altera Corp.
> 
> "Jan De Ceuster" <jandc@elis.ugent.be> wrote in message 
> news:cpkaji$9ma$1@gaudi2.UGent.be...
> 
>>>>* simulate netlist from core (yes I've got a license) : doesnt' work due 
>>>>to errors when trying to compile the thing.
>>>
>>>
>>>Consider posting the first few error messages.
>>
>>Yeah I know, I should give more information though no workarounds possbile 
>>(besides of editing the code) I think.
>>
>>here it is:
>>
>>ncvhdl: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc.
>>SIGNAL ww_\g_local_buffered_if:wdata_fifo\_data : std_logic_vector(29 
>>DOWNTO 0);
>>         |
>>I think that the _\ construction is illegal but to be honnest: I've no 
>>desire to dig in the vhdl reference to see who is right, Cadence and 
>>Synopsys versus Altera. 
> 
> 
> 

Hi Jan,

The construct written out in the vho netlist by Quartus was illegal,
and that is the reason for the message. This bug exists in Quartus II
4.0, 4.1 and 4.2. In each of these versions, you can workaround this in
one of two ways: The first described in the earlier post which is to
use Assignments->EDA Settings->Simulation, turn Map Illegal Characters
to on, OR the second which is Assignments->EDA
Settings->SimulationMaintain Hierarchy to off.

This bug will be fixed in Quartus II version 5.0.

> >>I think that the _\ construction is illegal but to be honnest: I've
no
> >>desire to dig in the vhdl reference to see who is right, Cadence
and
> >>Synopsys versus Altera.
> > 
> > 
> >

Hope this helps,
Subroto Datta
Altera Corp.