I'm trying to determine the delay curve of a particular path in a Virtex2Pro -5 from min timing to max, including all points in between. Obviously I can get the two end points (min and max) from the timing analyzer, but I assume that points between the two don't necessarily fall on a straight line. I considered also plotting the max timing of the other speed grades (-7 and -6), but I don't know what their relationship to each other is, so I wouldn't know exactly where to plot them relative to the -5 max endpoint. If anyone knows where performance graphs might exist in the Xilinx documenation, or what the relationship of speed grades to each other is, I'd be most appreciative of a response. Thanks!
Xilinx speed grading
Started by ●December 14, 2004
Reply by ●December 14, 20042004-12-14
Craig, remember that "speed grades" are an artificial way of segregating devices that are naturally made with a continuum of performance parameters. To accomodate the unavoidable manufacturing spread, IC manufacturers sort the devices into bins, so that they can guarantee performance, but also sell the devices that came out slow or "not so fast". In a perfect world, all parameters would scale perfectly, i.e. a device marked slow would have all its delays longer by the same factor, as compared to the devices labeled fast. The world is not perfect. The only thing you can be sure of is that you will never buy a part that is slower than its specification. All parameters will be better than the spec, but not all by the same percentage. Let me therefore discourage you from your elaborate plans. There is no simple answer. Peter Alfke ============================== Craig Conway wrote:> I'm trying to determine the delay curve of a particular path in a > Virtex2Pro -5 from min timing to max, including all points inbetween.> Obviously I can get the two end points (min and max) from the timing > analyzer, but I assume that points between the two don't necessarilyfall on> a straight line. I considered also plotting the max timing of theother> speed grades (-7 and -6), but I don't know what their relationship toeach> other is, so I wouldn't know exactly where to plot them relative tothe -5> max endpoint. > > If anyone knows where performance graphs might exist in the Xilinx > documenation, or what the relationship of speed grades to each otheris, I'd> be most appreciative of a response. > > Thanks!
Reply by ●December 15, 20042004-12-15
Peter, Thanks for responding. I understand pretty well the reasons behind speed binning and how artificial the boundaries are; however, there must be some overall criteria Xilinx uses to determine where to set those boundaries. When they bin their parts, they must be measuring several parameters and deciding that the aggregation of those measurements must be in a certain range to qualify as a -6. How does Xilinx decide what that range is? Craig "Peter" <peter@xilinx.com> wrote in message news:1103072858.873114.286400@f14g2000cwb.googlegroups.com...> Craig, remember that "speed grades" are an artificial way of > segregating devices that are naturally made with a continuum of > performance parameters. To accomodate the unavoidable manufacturing > spread, IC manufacturers sort the devices into bins, so that they can > guarantee performance, but also sell the devices that came out slow or > "not so fast". > In a perfect world, all parameters would scale perfectly, i.e. a device > marked slow would have all its delays longer by the same factor, as > compared to the devices labeled fast. > The world is not perfect. > The only thing you can be sure of is that you will never buy a part > that is slower than its specification. > All parameters will be better than the spec, but not all by the same > percentage. > Let me therefore discourage you from your elaborate plans. There is no > simple answer. > Peter Alfke > ============================== > Craig Conway wrote: >> I'm trying to determine the delay curve of a particular path in a >> Virtex2Pro -5 from min timing to max, including all points in > between. >> Obviously I can get the two end points (min and max) from the timing >> analyzer, but I assume that points between the two don't necessarily > fall on >> a straight line. I considered also plotting the max timing of the > other >> speed grades (-7 and -6), but I don't know what their relationship to > each >> other is, so I wouldn't know exactly where to plot them relative to > the -5 >> max endpoint. >> >> If anyone knows where performance graphs might exist in the Xilinx >> documenation, or what the relationship of speed grades to each other > is, I'd >> be most appreciative of a response. >> >> Thanks! >
Reply by ●December 15, 20042004-12-15
Craig, Before we fabricate the device (ie after we tape out) we examine the spice model corners, and decide what range of speed we can expect. We then decide to bin based on a yield goal into each speed bin. Once we have the parts, we fine tune the process with our fab partners to get what we designed to (after all, if the models don't match, how in the hell can we know if it will work?). Then, by construction, we have the yield (or better) to the bins we desired. Every technology node is different (process changes with each generation). So, take Peter's advice, Austin Craig Conway wrote:> Peter, > > Thanks for responding. I understand pretty well the reasons behind speed > binning and how artificial the boundaries are; however, there must be some > overall criteria Xilinx uses to determine where to set those boundaries. > When they bin their parts, they must be measuring several parameters and > deciding that the aggregation of those measurements must be in a certain > range to qualify as a -6. How does Xilinx decide what that range is? > > Craig > > "Peter" <peter@xilinx.com> wrote in message > news:1103072858.873114.286400@f14g2000cwb.googlegroups.com... > >>Craig, remember that "speed grades" are an artificial way of >>segregating devices that are naturally made with a continuum of >>performance parameters. To accomodate the unavoidable manufacturing >>spread, IC manufacturers sort the devices into bins, so that they can >>guarantee performance, but also sell the devices that came out slow or >>"not so fast". >>In a perfect world, all parameters would scale perfectly, i.e. a device >>marked slow would have all its delays longer by the same factor, as >>compared to the devices labeled fast. >>The world is not perfect. >>The only thing you can be sure of is that you will never buy a part >>that is slower than its specification. >>All parameters will be better than the spec, but not all by the same >>percentage. >>Let me therefore discourage you from your elaborate plans. There is no >>simple answer. >>Peter Alfke >>============================== >>Craig Conway wrote: >> >>>I'm trying to determine the delay curve of a particular path in a >>>Virtex2Pro -5 from min timing to max, including all points in >> >>between. >> >>>Obviously I can get the two end points (min and max) from the timing >>>analyzer, but I assume that points between the two don't necessarily >> >>fall on >> >>>a straight line. I considered also plotting the max timing of the >> >>other >> >>>speed grades (-7 and -6), but I don't know what their relationship to >> >>each >> >>>other is, so I wouldn't know exactly where to plot them relative to >> >>the -5 >> >>>max endpoint. >>> >>> If anyone knows where performance graphs might exist in the Xilinx >>>documenation, or what the relationship of speed grades to each other >> >>is, I'd >> >>>be most appreciative of a response. >>> >>> Thanks! >> > >
Reply by ●December 15, 20042004-12-15
Austin, just a quick question. Do many devices fail to meet your parametric specification, i.e. have performance that does not satisfy the lowest speed grade? Thanks, On Wed, 15 Dec 2004 08:02:39 -0800, Austin Lesea <austin@xilinx.com> wrote:>Craig, > >Before we fabricate the device (ie after we tape out) we examine the >spice model corners, and decide what range of speed we can expect. We >then decide to bin based on a yield goal into each speed bin. > >Once we have the parts, we fine tune the process with our fab partners >to get what we designed to (after all, if the models don't match, how in >the hell can we know if it will work?). Then, by construction, we have >the yield (or better) to the bins we desired. > >Every technology node is different (process changes with each generation). > >So, take Peter's advice, > >Austin > >Craig Conway wrote: >> Peter, >> >> Thanks for responding. I understand pretty well the reasons behind speed >> binning and how artificial the boundaries are; however, there must be some >> overall criteria Xilinx uses to determine where to set those boundaries. >> When they bin their parts, they must be measuring several parameters and >> deciding that the aggregation of those measurements must be in a certain >> range to qualify as a -6. How does Xilinx decide what that range is? >> >> Craig >> >> "Peter" <peter@xilinx.com> wrote in message >> news:1103072858.873114.286400@f14g2000cwb.googlegroups.com... >> >>>Craig, remember that "speed grades" are an artificial way of >>>segregating devices that are naturally made with a continuum of >>>performance parameters. To accomodate the unavoidable manufacturing >>>spread, IC manufacturers sort the devices into bins, so that they can >>>guarantee performance, but also sell the devices that came out slow or >>>"not so fast". >>>In a perfect world, all parameters would scale perfectly, i.e. a device >>>marked slow would have all its delays longer by the same factor, as >>>compared to the devices labeled fast. >>>The world is not perfect. >>>The only thing you can be sure of is that you will never buy a part >>>that is slower than its specification. >>>All parameters will be better than the spec, but not all by the same >>>percentage. >>>Let me therefore discourage you from your elaborate plans. There is no >>>simple answer. >>>Peter Alfke >>>============================== >>>Craig Conway wrote: >>> >>>>I'm trying to determine the delay curve of a particular path in a >>>>Virtex2Pro -5 from min timing to max, including all points in >>> >>>between. >>> >>>>Obviously I can get the two end points (min and max) from the timing >>>>analyzer, but I assume that points between the two don't necessarily >>> >>>fall on >>> >>>>a straight line. I considered also plotting the max timing of the >>> >>>other >>> >>>>speed grades (-7 and -6), but I don't know what their relationship to >>> >>>each >>> >>>>other is, so I wouldn't know exactly where to plot them relative to >>> >>>the -5 >>> >>>>max endpoint. >>>> >>>> If anyone knows where performance graphs might exist in the Xilinx >>>>documenation, or what the relationship of speed grades to each other >>> >>>is, I'd >>> >>>>be most appreciative of a response. >>>> >>>> Thanks! >>> >> >>
Reply by ●December 15, 20042004-12-15
On Wed, 15 Dec 2004 17:07:57 +0000, Jules P wrote:> Austin, > > just a quick question. Do many devices fail to meet your parametric > specification, i.e. have performance that does not satisfy the lowest > speed grade? > > Thanks, > > > > > On Wed, 15 Dec 2004 08:02:39 -0800, Austin Lesea <austin@xilinx.com> > wrote: > >>Craig, >> >>Before we fabricate the device (ie after we tape out) we examine the >>spice model corners, and decide what range of speed we can expect. We >>then decide to bin based on a yield goal into each speed bin. >> >>Once we have the parts, we fine tune the process with our fab partners >>to get what we designed to (after all, if the models don't match, how in >>the hell can we know if it will work?). Then, by construction, we have >>the yield (or better) to the bins we desired. >> >>Every technology node is different (process changes with each generation). >> >>So, take Peter's advice, >> >>Austin >> >>Craig Conway wrote: >>> Peter, >>> >>> Thanks for responding. I understand pretty well the reasons behind speed >>> binning and how artificial the boundaries are; however, there must be some >>> overall criteria Xilinx uses to determine where to set those boundaries. >>> When they bin their parts, they must be measuring several parameters and >>> deciding that the aggregation of those measurements must be in a certain >>> range to qualify as a -6. How does Xilinx decide what that range is? >>> >>> Craig >>> >>> "Peter" <peter@xilinx.com> wrote in message >>> news:1103072858.873114.286400@f14g2000cwb.googlegroups.com... >>> >>>>Craig, remember that "speed grades" are an artificial way of >>>>segregating devices that are naturally made with a continuum of >>>>performance parameters. To accomodate the unavoidable manufacturing >>>>spread, IC manufacturers sort the devices into bins, so that they can >>>>guarantee performance, but also sell the devices that came out slow or >>>>"not so fast". >>>>In a perfect world, all parameters would scale perfectly, i.e. a device >>>>marked slow would have all its delays longer by the same factor, as >>>>compared to the devices labeled fast. >>>>The world is not perfect. >>>>The only thing you can be sure of is that you will never buy a part >>>>that is slower than its specification. >>>>All parameters will be better than the spec, but not all by the same >>>>percentage. >>>>Let me therefore discourage you from your elaborate plans. There is no >>>>simple answer. >>>>Peter Alfke >>>>============================== >>>>Craig Conway wrote: >>>> >>>>>I'm trying to determine the delay curve of a particular path in a >>>>>Virtex2Pro -5 from min timing to max, including all points in >>>> >>>>between. >>>> >>>>>Obviously I can get the two end points (min and max) from the timing >>>>>analyzer, but I assume that points between the two don't necessarily >>>> >>>>fall on >>>> >>>>>a straight line. I considered also plotting the max timing of the >>>> >>>>other >>>> >>>>>speed grades (-7 and -6), but I don't know what their relationship to >>>> >>>>each >>>> >>>>>other is, so I wouldn't know exactly where to plot them relative to >>>> >>>>the -5 >>>> >>>>>max endpoint. >>>>> >>>>> If anyone knows where performance graphs might exist in the Xilinx >>>>>documenation, or what the relationship of speed grades to each other >>>> >>>>is, I'd >>>> >>>>>be most appreciative of a response. >>>>> >>>>> Thanks! >>>> >>> >>>If they had a significant number of parts that failed to meet the lowest speed grade but otherwise worked they would just introduce a lower speed grade. In fact Xilinx offers parts that don't work completely. Some parts have slight defects which effect only a subset of designs. You can give Xilinx a bit file and a set of test patterns and they will test their slightly defective parts to see if they will work for your application, if they do they will sell them to you at a huge discount. It's the same principle as hog butchers, they sell everything except the squeal.
Reply by ●December 15, 20042004-12-15
"everything except the squeal"? Now that is pretty graphic. EasyPath(tm) is no different that selling an FPGA that has a laser fuse blown to replace a defective column of logic. Gee, I wonder who does that with every part they sell? Get over it: a few bad memory bits (out of 20 million) is not a "slightly defective" part -- it is >99.99985% perfect. Austin
Reply by ●December 15, 20042004-12-15
Austin Lesea wrote:> > "everything except the squeal"? > > Now that is pretty graphic. > > EasyPath(tm) is no different that selling an FPGA that has a laser fuse > blown to replace a defective column of logic. > > Gee, I wonder who does that with every part they sell? > > Get over it: a few bad memory bits (out of 20 million) is not a > "slightly defective" part -- it is >99.99985% perfect.Isn't being 99.99985% perfect like being 0.00015% pregnant? ;) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●December 15, 20042004-12-15
Reply by ●December 15, 20042004-12-15
Rick, The simple answer? No, it is not. One bad bit doth not a bad chip make. If it did, the entire RAM business would be out of business. All RAM (and EPROM) use redundant rows or columns, and redundant repair (or self repair) structures. Music CD's run with error correction correcting errors all the time (there is practically no interval where there is a single packet with 0 errors). Cell phones work with forward error correction, and they too run in the errored region all the time. Austin rickman wrote:> Austin Lesea wrote: > >>"everything except the squeal"? >> >>Now that is pretty graphic. >> >>EasyPath(tm) is no different that selling an FPGA that has a laser fuse >>blown to replace a defective column of logic. >> >>Gee, I wonder who does that with every part they sell? >> >>Get over it: a few bad memory bits (out of 20 million) is not a >>"slightly defective" part -- it is >99.99985% perfect. > > > Isn't being 99.99985% perfect like being 0.00015% pregnant? ;) >
