New release of SystemC to Verilog translator

Started by Javier Castillo December 20, 2004

OpenSoc Design has released version 0.2 of its SystemC to Verilog 
Synthesizable subset translator.

This release includes:
- Support for C++ enumerate data types 
- More SystemC constructions supported 
- Directives to support custom translation as:
-//Translate off, //Translate on: To avoid translate some areas of code
-//Verilog, //EndVerilog: To indicate the translator to not translate the 
code between the directives 

You can download it for free from