Xilinx + Modelsim *Please Help Tonight*

I am trying to use modelsim to do a timing simulation on a VHDL file I 
generated using xilinx. I generated the: ecc.sim.sdf and the ecc_sim.vhdl.

However in modelsim with I use these commands it give me an error at the 5th 
command. It will not vsim.

cd {c:/ecc/lab1test/ecc_multiply}
vlib work
vmap simprim c:/modeltech_6.0b/examples/Modeltech_6.0bxilinx/simprim
vcom ecc_sim.vhd
vsim -sdftyp /=c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf work.multiply


The error I get is:

 ** Warning: (vsim-SDF-3440) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf: 
Failed to find any of the 85 instances from this file.
# ** Warning: (vsim-SDF-3442) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf: Try 
instance '/multiply/nlwblockroc'. It contains all instance paths from this 
file.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file 
"c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf".
#    Time: 0 ns  Iteration: 0  Region: /multiply  File: ecc_sim.vhd


Please help.

I am using modelsim 6.0b 

Ricky Stern wrote:

>  ** Warning: (vsim-SDF-3440) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf:
> Failed to find any of the 85 instances from this file.
> # ** Warning: (vsim-SDF-3442) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf: Try
> instance '/multiply/nlwblockroc'. It contains all instance paths from this
> file.
> # ** Error: (vsim-SDF-3445) Failed to parse SDF file
> "c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf".
> #    Time: 0 ns  Iteration: 0  Region: /multiply  File: ecc_sim.vhd

These errors indicate you are not using correct combination of post annotated
VHDL file and SDF file. You might have multiple versions of VHDL and SDF file
which aren't co-relating i.e. not generated from the same design.
Also, what version of Xilinx tools are you using?

Regards
Vikram

xilinx 5.3

I am using the post place and route to create a modelsim vhdl and sdf file 
that I named myself  so I am use I am using the right ones.

thanks

"Vikram Pasham" <Vikram.Pasham@xilinx.com> wrote in message 
news:41D4EF0A.A899ACB4@xilinx.com...
>
>
> Ricky Stern wrote:
>
>>  ** Warning: (vsim-SDF-3440) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf:
>> Failed to find any of the 85 instances from this file.
>> # ** Warning: (vsim-SDF-3442) c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf: 
>> Try
>> instance '/multiply/nlwblockroc'. It contains all instance paths from 
>> this
>> file.
>> # ** Error: (vsim-SDF-3445) Failed to parse SDF file
>> "c:/ecc/lab1test/ecc_multiply/ecc_sim.sdf".
>> #    Time: 0 ns  Iteration: 0  Region: /multiply  File: ecc_sim.vhd
>
> These errors indicate you are not using correct combination of post 
> annotated
> VHDL file and SDF file. You might have multiple versions of VHDL and SDF 
> file
> which aren't co-relating i.e. not generated from the same design.
> Also, what version of Xilinx tools are you using?
>
> Regards
> Vikram
>