Hi all! I am currently looking for an application note, a tech report or anything else that deals with Xilinx Spartan2 bitstream structure in order to edit bitstreams for this FPGA. Someone has ever tried to do that ? Cheers, Gr�gory
Editing bitstream
Started by ●January 10, 2005
Reply by ●January 10, 20052005-01-10
Gregory, you have to be more specific about what you want to edit: BlockRAM content: easy LUTs: not too difficult Interconnect structure: forget it Peter Alfke
Reply by ●January 10, 20052005-01-10
In article <1105379893.785166.222330@c13g2000cwb.googlegroups.com>, Peter Alfke <peter@xilinx.com> wrote:>Gregory, you have to be more specific about what you want to edit: >BlockRAM content: easy >LUTs: not too difficult >Interconnect structure: forget itIf you REALLY want to edit interconnect structure on a Xilinx FPGA, use one supported by JBits. But you really, REALLY don't want to. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
Reply by ●January 10, 20052005-01-10
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:cruiv3$2n6e$1@agate.berkeley.edu...> If you REALLY want to edit interconnect structure on a Xilinx FPGA, > use one supported by JBits. But you really, REALLY don't want to.Is there a practical reason to do so?? Cant think of such a reason. Regards Falk
Reply by ●January 10, 20052005-01-10
Peter Alfke wrote:> Gregory, you have to be more specific about what you want to edit: > BlockRAM content: easy > LUTs: not too difficult > Interconnect structure: forget it > > Peter Alfke >LUTs. But thanks, xapp151 came and told me the truth about it :) But it does not seem to be "not too difficult" as you say. I need to make it completely automatic through a C program. Maybe do you know any tutorial or further paper or application note concerning this problem ?
Reply by ●January 10, 20052005-01-10
In article <34g7sqF49urriU1@individual.net>, Falk Brunner <Falk.Brunner@gmx.de> wrote:>> If you REALLY want to edit interconnect structure on a Xilinx FPGA, >> use one supported by JBits. But you really, REALLY don't want to. > >Is there a practical reason to do so?? >Cant think of such a reason.A researcher working on routing algorithms. A researcher looking to reroute designs to better handle partial configuration. A researcher looking at how to deal with a large board of flawed FPGAs (a'la the old HP system), especially with easypath parts testing the LUT fully but not fully testing the interconnect.>Regards >Falk > > > > >-- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
Reply by ●January 11, 20052005-01-11
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:crv421$79c$1@agate.berkeley.edu...> >Is there a practical reason to do so?? > >Cant think of such a reason. > > A researcher working on routing algorithms. > > A researcher looking to reroute designs to better handle partial > configuration. > > A researcher looking at how to deal with a large board of flawed FPGAs > (a'la the old HP system), especially with easypath parts testing the > LUT fully but not fully testing the interconnect.But this all is stuff done only by the Xilinx folks or people working close to Xilinx to improve the design flow tools (map/ p&R). And those guy for sure have much more detailed information (and tools) about FPGA connectivity. No normal mortal, ahhh user, does this kind of stuff, not even advanced users. But I wont stop anyone. Regards Falk
Reply by ●January 11, 20052005-01-11
In article <34ike7F4a19aaU1@individual.net>, Falk Brunner <Falk.Brunner@gmx.de> wrote:>But this all is stuff done only by the Xilinx folks or people working close >to Xilinx to improve the design flow tools (map/ p&R). And those guy for >sure have much more detailed information (and tools) about FPGA >connectivity. No normal mortal, ahhh user, does this kind of stuff, not >even advanced users. >But I wont stop anyone.Uh, you'd be suprised what a researcher would want to do. EG, one research bit I did loaded Xilinx designs after placement but before routing, ripped up all the registers, duplicated them for C-slowing, retimed, reinserted all the new registers, and wrote back out the placement. I could EASILY see an interesting research project which "meer mortal researchers" could attempt which would be take a bunch of easypath parts, map the actual defects, and route around defets albeit at a performance penalty. It might be interesting to see if you colud use this to build a multi-teraflop vector supercomputer on a decent budget. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
Reply by ●January 11, 20052005-01-11
Nicholas Weaver wrote:>> I could EASILY see an interesting research project which "meermortal> researchers" could attempt which would be take a bunch of easypath > parts, map the actual defects, and route around defets albeit at a > performance penalty.Nick, as you know, there is no "bunch of EasyPath parts". By the nature of the beast, each and every one part is different. That makes your suggestion a formidably inefficient job... Peter Alfke
Reply by ●January 12, 20052005-01-12
"Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> schrieb im Newsbeitrag news:cs16o1$2619$1@agate.berkeley.edu...> Uh, you'd be suprised what a researcher would want to do. EG, one > research bit I did loaded Xilinx designs after placement but before > routing, ripped up all the registers, duplicated them for C-slowing, > retimed, reinserted all the new registers, and wrote back out the > placement. > > I could EASILY see an interesting research project which "meer mortal > researchers" could attempt which would be take a bunch of easypath > parts, map the actual defects, and route around defets albeit at a > performance penalty.As I said, I wont stop anyone. But this looks like something for someone with too much free time on hands. No offence intended ;-) Regards Falk
