I am designing an encryption algorithm using VHDL & targetting it to Stratix EP1S10F780C6.The problem is that post P&R simulation results are not correct.however when i target to Stratix EP1S10F780C5, i get the correct encrypted/decrypted output.How does the speed grade affect the post P&R output.The device i m using is the same.only spped grade is diffeterent.I am using Quartus synthesis tools for synthesising the code...pls help
altera stratix problem
Started by ●January 11, 2005
Reply by ●January 11, 20052005-01-11
Hi vlsi_learner,> I am designing an encryption algorithm using VHDL & targetting it to > Stratix EP1S10F780C6.The problem is that post P&R simulation results > are not correct.however when i target to Stratix EP1S10F780C5, i get > the correct encrypted/decrypted output.How does the speed grade affect > the post P&R output.The device i m using is the same.only spped grade > is diffeterent.I am using Quartus synthesis tools for synthesising the > code...pls helpHave you looked at the timing report to see if there were no red lines in any of the timing specs? Rgds, Ben
Reply by ●January 11, 20052005-01-11
hi Ben i have compared the timing reports for both the cases ie with Stratix EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same except that the critical path delay is different for EP1S10F780C6 : critical path delay is 10.647 ns total cell delay is 4.956 ns total interconnect delay is 5.691 ns for EP1S10F780C5 : critical path delay is 9.468 ns total cell delay is 4.420 ns total interconnect delay is 5.048 ns wat should i do??? the results are correct for EP1S10F780C5..how should i reduce the critical path delay for stratix EP1S10F780C6 Ben Twijnstra wrote:> Hi vlsi_learner, > > > I am designing an encryption algorithm using VHDL & targetting itto> > Stratix EP1S10F780C6.The problem is that post P&R simulationresults> > are not correct.however when i target to Stratix EP1S10F780C5, iget> > the correct encrypted/decrypted output.How does the speed gradeaffect> > the post P&R output.The device i m using is the same.only sppedgrade> > is diffeterent.I am using Quartus synthesis tools for synthesisingthe> > code...pls help > > Have you looked at the timing report to see if there were no redlines in> any of the timing specs? > > Rgds, > > > Ben
Reply by ●January 11, 20052005-01-11
Hi vlsi_learner, Quartus II 4.1 and newer versions of Software has an application called Timing Optimization Advisor under the Tools menu. First compile the design and then click on Tools->Timing Optimization Advisor. On the left panel of the advisor, you will find a list of recommendations that can be used for optimizing timing, based on the type of timing requirements and second based on the order in which you should try these recommendations. If you go the top of the Timing Optimization Advisor Left panel and click on the Timing Summary you should see a summary of your timing report. The detailed Timing report is available in the compilation report window. Hope this helps. - Subroto Datta Altera Corp. "vlsi_learner" <bajajk@gmail.com> wrote in message news:1105428506.583848.218950@f14g2000cwb.googlegroups.com...> hi Ben > > i have compared the timing reports for both the cases ie with Stratix > EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same > except that the critical path delay is different > > for EP1S10F780C6 : critical path delay is 10.647 ns > total cell delay is 4.956 ns > total interconnect delay is 5.691 ns > > for EP1S10F780C5 : critical path delay is 9.468 ns > total cell delay is 4.420 ns > total interconnect delay is 5.048 ns > > wat should i do??? the results are correct for EP1S10F780C5..how should > i reduce the critical path delay for stratix EP1S10F780C6> Ben Twijnstra wrote: >> Hi vlsi_learner, >>......>> Have you looked at the timing report to see if there were no red > lines in >> any of the timing specs? >> >> Rgds, >> >> >> Ben >
Reply by ●January 11, 20052005-01-11
Hi vlsi_learner,> hi Ben > > i have compared the timing reports for both the cases ie with Stratix > EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same > except that the critical path delay is different > > for EP1S10F780C6 : critical path delay is 10.647 ns > total cell delay is 4.956 ns > total interconnect delay is 5.691 ns > > for EP1S10F780C5 : critical path delay is 9.468 ns > total cell delay is 4.420 ns > total interconnect delay is 5.048 ns > > wat should i do??? the results are correct for EP1S10F780C5..how should > i reduce the critical path delay for stratix EP1S10F780C6If your clock frequency is 100MHz, your clock period in 10ns. Ergo, the C6 is too slow, and the C5 meets timing. From what I gather from your story, you don't seem to have put any information regarding clock frequency into your Quartus project. This means that Quartus will compile the circuit, do a few P&R iterations, and then finishes, telling what it thought up as a possible solution. Once Quartus knows about your minimum clock frequency and, probably, the Tsu and Tco constraints (I usually set them to about 2/3 of the clock period if there are no special demands) it will try to meet these constraints and will telly if it hasn't been able to find a P&R solution that met your requirements. If you have indeed not entered any clock frequency constraints in your project, you can do so by clicking "Assignments" on the menu bar and selecting "Timing Wizard". Just follow the instructions. Another solution I have seen, but definitely not one for production environments, is to apply a healthy dose of cold spray to the FPGA if the circuit doesn't violate timing constraints too badly. The lower temperature will make circuit timing faster. As stated, good for experimenting and testing your algorithm, but not for an end product, unless of course you want to ship your crypto processor with a lifetime supply of cold spray ;-) Best regards, Ben
Reply by ●January 14, 20052005-01-14
This is good advice. If you have no timing constraints, Quartus will perform only minimal timing optimization on a design during place and route if you have "Auto Fit" (the default) selected. So you should definitely enter your required clock frequencies into Quartus, using the method Ben describes. At that point Quartus will flag timing violations (check the timing analyzer section in the compilation report) and will work to optimize the design to meet your constraints, so violations are less likely. Vaughn Altera [v b e t z (at) altera.com] "Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:ooXEd.314728$lN.313548@amsnews05.chello.com...> Hi vlsi_learner, > > > hi Ben > > > > i have compared the timing reports for both the cases ie with Stratix > > EP1S10F780C6 & Stratix EP1S10F780C5.The resources etc used are all same > > except that the critical path delay is different > > > > for EP1S10F780C6 : critical path delay is 10.647 ns > > total cell delay is 4.956 ns > > total interconnect delay is 5.691 ns > > > > for EP1S10F780C5 : critical path delay is 9.468 ns > > total cell delay is 4.420 ns > > total interconnect delay is 5.048 ns > > > > wat should i do??? the results are correct for EP1S10F780C5..how should > > i reduce the critical path delay for stratix EP1S10F780C6 > > If your clock frequency is 100MHz, your clock period in 10ns. Ergo, the C6 > is too slow, and the C5 meets timing. > > From what I gather from your story, you don't seem to have put any > information regarding clock frequency into your Quartus project. Thismeans> that Quartus will compile the circuit, do a few P&R iterations, and then > finishes, telling what it thought up as a possible solution. > > Once Quartus knows about your minimum clock frequency and, probably, theTsu> and Tco constraints (I usually set them to about 2/3 of the clock periodif> there are no special demands) it will try to meet these constraints and > will telly if it hasn't been able to find a P&R solution that met your > requirements. > > If you have indeed not entered any clock frequency constraints in your > project, you can do so by clicking "Assignments" on the menu bar and > selecting "Timing Wizard". Just follow the instructions. > > Another solution I have seen, but definitely not one for production > environments, is to apply a healthy dose of cold spray to the FPGA if the > circuit doesn't violate timing constraints too badly. The lowertemperature> will make circuit timing faster. > > As stated, good for experimenting and testing your algorithm, but not foran> end product, unless of course you want to ship your crypto processor witha> lifetime supply of cold spray ;-) > > Best regards, > > > Ben >
Reply by ●January 18, 20052005-01-18
hi Yes i was not giving any constraints while running the design.Actually i have Quartus version 4.0 which does not provide the facility of Timing Optimization advisor.so could not use that facility. Now when i am giving the constraints as Fmax =100 Mhz & tsu,tco constraint as suggested by Ben,i get Timing violations.How do i remove the Timing errors?? If i reduce the value of Fmax, again i get correct output for Stratix EP1S10F780C5 but not for EP1S10F780C6. I have broken down the combinational path by inserting FF's also?? Another thing i am using Asynchronous memory in my design (Look up tables).Will that have a negative impact on the result when targeting to Stratix device??
Reply by ●January 18, 20052005-01-18
One more thing if you could help.. I am using Async memory in my logic..This memory is being automatically inferenced by the Quartus tool (alt_syncram function).I am just coding the async memory using VHDL. For Stratix EP1S10F780C5, the largest memory to memory delay is 9.7 ns while for EP1S10F780C6 the largest memory to memory delay is 10.809 ns. How can i reduce this????? vlsi_learner wrote:> hi > Yes i was not giving any constraints while running thedesign.Actually> i have Quartus version 4.0 which does not provide the facility of > Timing Optimization advisor.so could not use that facility. > Now when i am giving the constraints as Fmax =100 Mhz & tsu,tco > constraint as suggested by Ben,i get Timing violations.How do iremove> the Timing errors?? > > If i reduce the value of Fmax, again i get correct output for Stratix > EP1S10F780C5 but not for EP1S10F780C6. I have broken down the > combinational path by inserting FF's also?? > > Another thing i am using Asynchronous memory in my design (Look up > tables).Will that have a negative impact on the result when targeting > to Stratix device??