Hi, all: Implementing a UART(asic core) into XILINX Virtex2 3000-5. Due to 99% slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns). On debuging, the UART is work well on some boards, however, occur error on other boards. And when I add a skew constraint to limit the skew below 1ns, all boards is ok. I hope to know, does par tools do setup / hold check with skew analyse. My current mapping tools is ISE5.2.03. regards, seyior
Large SKEW kill UART?
Started by ●January 11, 2005
Reply by ●January 11, 20052005-01-11
Hi Seyior, Are you trolling? ;-) A cursory search back through this newsgroup with Google will show that 'gated clocks' are anathema to everyone here. DON'T DO IT! Cheers, Syms. <seyior> wrote in message news:ee8b070.-1@webx.sUN8CHnE...> Hi, all: > > Implementing a UART(asic core) into XILINX Virtex2 3000-5. Due to 99%slices is used (2 slices is unused), the skew of the gated clock in UART is a little large (2-3 ns).> > On debuging, the UART is work well on some boards, however, occur error onother boards. And when I add a skew constraint to limit the skew below 1ns, all boards is ok.> > I hope to know, does par tools do setup / hold check with skew analyse. Mycurrent mapping tools is ISE5.2.03.> > regards, seyior