A master thesis comparing the LEON2, Microblaze and Openrisc-1200 processors has been carried out by two students from the Chalmers University in Sweden. The final report is now available online at: http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf . Jiri Gaisler Gaisler Research
Comparison of LEON2, Microblaze and Openrisc processors
Started by ●January 19, 2005
Reply by ●January 19, 20052005-01-19
On Wed, 19 Jan 2005 02:29:02 -0800, jiri_gaisler wrote:> A master thesis comparing the LEON2, Microblaze and Openrisc-1200 > processors has been carried out by two students from the Chalmers > University in Sweden. The final report is now available online at: > > http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf > . >I would have thought that a comparison of synthesisable cores would have included a Nios 2 as well, and would have included other fpga targets - the conclusions might have been wildly different if an Altera fpga were used, or even if a different Xilinx fpga were used rather than just the one Virtex II. The thesis claims to cover portability, yet only considers "porting" the cores to a single Virtex II board! As open designs, the Leon2 and Openrisc cpus are a world apart on portability compared to vendor-specific cores like the Microblaze and the Nios. I think it is also important to make version information clear - I don't know details about the processors here, but the Nios family has changed dramatically in the year or so that I've been using it, and such comparisons are only valid for a particular generation of the cores.
Reply by ●January 19, 20052005-01-19
During the mentioned study, we were limited to a Virtex-II board and could thus not evaluate the Nios processor. However, we have ordered an Altera Cyclone board with the Nios-II design kit. A follow-up study will be made this spring, evaluating Nios-II and LEON2 on Altera hardware. It is not possible to evaluate Microblaze and Nios on the same hardware since only mapped netlists are provided with their design kits. Jiri.
Reply by ●January 19, 20052005-01-19
On Wed, 19 Jan 2005 07:03:27 -0800, jiri_gaisler wrote:> During the mentioned study, we were limited to a Virtex-II board and > could thus not evaluate the Nios processor. However, we have ordered > an Altera Cyclone board with the Nios-II design kit. A follow-up > study will be made this spring, evaluating Nios-II and LEON2 on > Altera hardware. It is not possible to evaluate Microblaze and Nios > on the same hardware since only mapped netlists are provided with > their design kits. > > Jiri.I appreciate that you can't evaluate a Nios 2 on a Xilinx fpga, or a Microblaze on an Altera fpga (or either on other fpga's), so any sort of comparison matrix is going to have gaps in it. I also appreciate that testing different cpus on different fpgas takes time and costs money (unless you can borrow the boards). I just object to the idea of a thesis claiming to be a general comparison of synthesizable cpu cores but missing out what is probably the most commonly used core, and which claims to address portability yet limits this to a single fpga from a single vendor. At the very least, your thesis should make these limitations abundantly clear, and you could give limited information (such as performance and size estimates from the design software) for high and low-end chips. Still, the paper provides some useful information for people looking at these cores, and it's good of you to make it publicly available. mvh., David
Reply by ●January 19, 20052005-01-19
jiri_gaisler wrote:> A master thesis comparing the LEON2, Microblaze and Openrisc-1200 > processors has been carried out by two students from the Chalmers > University in Sweden. The final report is now available online at: > > http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdfOn page 5, they have an estimate of 15 million gates for a 32x32 multiplier (1 clock). Anybody knows how they came to this one ?
Reply by ●January 19, 20052005-01-19
"jiri_gaisler" <jiri@gaisler.com> skrev i meddelandet news:1106130542.868417.48750@c13g2000cwb.googlegroups.com...> A master thesis comparing the LEON2, Microblaze and Openrisc-1200 > processors has been carried out by two students from the Chalmers > University in Sweden. The final report is now available online at: > > http://www.gaisler.com/doc/Evaluation_of_synthesizable_CPU_cores.pdf > . > > Jiri Gaisler > > Gaisler Research >The big question is if it makes sense to use 2-8000 CLBs for a CPU in the first place? Reasonably, such a chip will need to have an external flash memory and the pins between the FPGA and the Flash. Think it will be hard to pricewise meet a hardwired solution with internal/external CPU. Think it would be nice to compare with a solution based on the AT91FR40162 (10 x 10 mm) running 60 MIPS at 20 mW with a smaller FPGA. The FPSLIC and some PowerPC equipped Virtex are another approach which should be more cost effective for most applications One advantage of implementing in FPGA, is it allows you to migrate if chips become obsolete. Then again, going with a Microblaze will force you into Xilinx FPGAs, and if you choose the Leon/OpenRISC, the core is more expensive. Building your own chip, is of course more fun! -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.
Reply by ●January 20, 20052005-01-20
>Reasonably, such a chip will need to have an external flash memory >and the pins between the FPGA and the Flash.Good point, but... It depends upon the problem. Lots of interesting problems will fit into on-chip RAM. They might fit better into a special purpose CPU. That costs more design time. External serial flash will be horribly slow, but might be good enough for some problems. Only takes a few pins. You could use on chip RAM for a cache or load it explicitly (bank switching). -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●January 20, 20052005-01-20
Hal Murray wrote:>>Reasonably, such a chip will need to have an external flash memory >>and the pins between the FPGA and the Flash. > > > Good point, but... It depends upon the problem. > > Lots of interesting problems will fit into on-chip RAM. > They might fit better into a special purpose CPU. That > costs more design time.The PicoBlaze, and tiniest variant of NIOS are interesting forthis> > External serial flash will be horribly slow, but might be good > enough for some problems. Only takes a few pins. You could > use on chip RAM for a cache or load it explicitly (bank switching).Yes, a core that used 50MHz SPI memory, and was optimised for serial-code fetch could be quite interesting.... -jg
Reply by ●January 20, 20052005-01-20
I have an unpublished success-story about using MicroBlaze in Commercial Product using XC2S100 with no external memory. Thats I think the smallest FPGA where Microblaze (at least Xilinx version!) can be used. The open- source MicroBlaze used in simple controller fashion could possible be useable in S50 too. Or small smallest Cyclone :) And some comments to previous posters it is possible: 1) to run NIOS-II in Xilinx FPGA 2) to run Microblaze in Altera FPGA well at least I have tried both :) Antti
Reply by ●January 20, 20052005-01-20
"Jim Granville" <no.spam@designtools.co.nz> skrev i meddelandet news:41ef3cfd$1@clear.net.nz...> Hal Murray wrote: > >>Reasonably, such a chip will need to have an external flash memory > >>and the pins between the FPGA and the Flash. > > > > > > Good point, but... It depends upon the problem. > > > > Lots of interesting problems will fit into on-chip RAM. > > They might fit better into a special purpose CPU. That > > costs more design time.One of the few reasons why you would want to have a soft processor today, is if you can boost your application through a non standard instruction set. Why would you choose an FPGA with a soft Microblaze/Leon/OpenRISC over an FPGA with a hardwired Microblaze/Leon/OpenRISC? If you come to the conclusion that a hardwired Leon is better than a soft one, then you need to ask yourself, if it is very important having a Leon, or will an external ARM7 chip do? The AT91FR40162 is 10 x 10 mm so it is not a lot of board space yuou can save by just having an external flash. If you had a low cost coverification tool for the specific architecture then it is easier to develop the FPGA, and this could be one motivation. I have not heard about coverification for the cores mentioned above though. A multichip package with flash and FPGA would make the proposal more attractive if you need certain combinations not available in std micros like PCI bus enabled controller. This would result in smaller board space. You can of course do a multichip FPGA + Flash Micro, but market might be smaller> The PicoBlaze, and tiniest variant of NIOS are interesting forthis > > > > > External serial flash will be horribly slow, but might be good > > enough for some problems. Only takes a few pins. You could > > use on chip RAM for a cache or load it explicitly (bank switching).You mean an FPSLIC ;-) Loads from -- Best Regards Ulf at atmel dot com These comments are intended to be my own opinion and they may, or may not be shared by my employer, Atmel Sweden.
