SystemACE and Jtag

I'm working on a Xilinx demonstration board equipped with a jtag chain 
including a SystemACE CF and a Virtex-II FPGA.
My goal is to configure the FPGA via Jtag bypassing the SystemACE.
Unfortunaly, after the hardware reset, the SystemACE is configured by 
default to look for a bitstream on the Compact Flash: in this way, it 
doesn't allow me to
reach the FPGA through the Jtag. I have to use Impact software to 
configure for the first time, and then I can access to FPGA. So, I think 
that Impact configures
the SystemACE in order to transfer data to FPGA.
It's possible to program the SystemACE via Jtag?On Xilinx 080 Datasheet 
(SystemACE CF solution) I can find only 4 instructions (idcode, sample, 
extest, bypass);
in adding to this, it seems that Jtag Configuration Register is not present.
Are there any others not documented commands which allow me to configure 
SystemAce (for example cgfin and cfgout)? Otherwise, have anybody a 
solution for my problem?
Thank you very much.
Salvatore

The CF from the SystemACE CF is not configurable via boundary-scan.  It 
can only be configured using a CompactFlash programming cable through 
your PC.  The CF could, however, be addressed using an embedded 
processor using the microprocessor port on the controller chip.

I think, though, that you have misunderstood the interaction between 
SystemACE CF and the FPGA.  You should be able to reach the FPGA through 
the boundary-scan of the SystemACE CF controller in all scenarios

Scarex wrote:
> I'm working on a Xilinx demonstration board equipped with a jtag chain 
> including a SystemACE CF and a Virtex-II FPGA.
> My goal is to configure the FPGA via Jtag bypassing the SystemACE.
> Unfortunaly, after the hardware reset, the SystemACE is configured by 
> default to look for a bitstream on the Compact Flash: in this way, it 
> doesn't allow me to
> reach the FPGA through the Jtag. I have to use Impact software to 
> configure for the first time, and then I can access to FPGA. So, I think 
> that Impact configures
> the SystemACE in order to transfer data to FPGA.
> It's possible to program the SystemACE via Jtag?On Xilinx 080 Datasheet 
> (SystemACE CF solution) I can find only 4 instructions (idcode, sample, 
> extest, bypass);
> in adding to this, it seems that Jtag Configuration Register is not 
> present.
> Are there any others not documented commands which allow me to configure 
> SystemAce (for example cgfin and cfgout)? Otherwise, have anybody a 
> solution for my problem?
> Thank you very much.
> Salvatore

Neil Glenn Jacobson ha scritto:
> The CF from the SystemACE CF is not configurable via boundary-scan.  It 
> can only be configured using a CompactFlash programming cable through 
> your PC.  The CF could, however, be addressed using an embedded 
> processor using the microprocessor port on the controller chip.
> 
> I think, though, that you have misunderstood the interaction between 
> SystemACE CF and the FPGA.  You should be able to reach the FPGA through 
> the boundary-scan of the SystemACE CF controller in all scenarios
> 

Hi Neil,
today I've solved the problem. Using Jbits on jtag chain, I've 
discovered I've to give to SystemACE the JSTART command, like FPGA, even 
if in the SystemACE Datasheet Xilinx doesn't report this command.

Bye
Scarex