Xilinx Sum in VHDL

Hello FPGA group,

I have to create this sum
A+2B+C
where A, B, and C are 8 bit std_logic_vector
as part of a Sobel function.

What is the best way of doing this?

I have been able to get correct results
with the following:

 signal  sum : std_logic_vector(9 downto 0);
 begin
 sum <= ("00"&in1) + ('0'&in2&'0') + ("00"&in3) ;

However I find this code looks a bit sticky and I
wonder if it may be synthesizing 10 bit adders to
do 8 bit work.  The Map report says that I am
using 15 LUTs and 9 slices.

Spartan 3, and most of the other Xilinx parts, have an
ADD8 macro, according to the library guide, but I
couldn't find how to instantiatie this as a component.
Are macros components?

Thanks for your consideration,

Brad Smallridge
brad at www.aivision.com

Brad Smallridge wrote:

> However I find this code looks a bit sticky and I
> wonder if it may be synthesizing 10 bit adders to
> do 8 bit work.  The Map report says that I am
> using 15 LUTs and 9 slices.

Umm, you're *not* 'doing 8 bit work'?!?

-- 
|              Mark McDougall                | "Electrical Engineers do it
|         <http://to be announced>           |   with less resistance!"

> Umm, you're *not* 'doing 8 bit work'?!?

Hello Mark,

OK, it seems to me that the best solution is
one eight bit adder with a carry, going into
a nine bit adder (maybe not if I don't care about
the lower bits) with a carry, giving me a 10 bit sum.

My question is (was), does this VHDL give me
10 bit adders throughout, instead of an optimised
solution, on a Xilinx XST platform?

And is this, overall, the best way of doing a sum
like this?

Mark, is that clearer?

Brad




 

Brad Smallridge wrote:


> OK, it seems to me that the best solution is
> one eight bit adder with a carry, going into
> a nine bit adder (maybe not if I don't care about
> the lower bits) with a carry, giving me a 10 bit sum.

> My question is (was), does this VHDL give me
> 10 bit adders throughout, instead of an optimised
> solution, on a Xilinx XST platform?

 From the software I know, it likely will generate that, but
during place and route any redundant gates will be removed.

The result, then, should be just what you say, unless the
addition is done in a different order.

Systems I know about will remove FF's with constant inputs,
combine registers with the same inputs, remove gates where
all the inputs, or all but one are constant, eliminate
inverters by inverting the output of the preceding device,
and probably more.  Usually there are messages telling what
it is doing.

-- glen

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10v0fe7igutmt55@corp.supernews.com...
[ snip ]
> OK, it seems to me that the best solution is
> one eight bit adder with a carry, going into
> a nine bit adder (maybe not if I don't care about
> the lower bits) with a carry, giving me a 10 bit sum.
>
> My question is (was), does this VHDL give me
> 10 bit adders throughout, instead of an optimised
> solution, on a Xilinx XST platform?
>
> And is this, overall, the best way of doing a sum
> like this?
[ snip ]

Since your synthesis shows 15 LUTs used, I expect that the sum is the
cascade of 2 9-bit adders.  Consider that A+C is a 9 bit value but the LSbit
is added to zero so it can pass straight through without going to another
adder.  The second adder takes the top 8 bits of the 9-bit A+C result and
adds it to the 8-bit shifted B value.  I would have expected 16 LUTs in the
two 8-bit adders (with "free" carry-outs) but the synthesizer might have
combined something for the LSbits saving you a LUT.

I use Synplify for my synthesis and go to the HDL Analyzer to check the
synthesizer's implementation when I have efficiency concerns.  I get full
visibility into the technology level implementation, no questions.

You're probably doing great on efficiency.

"John_H" <johnhandwork@mail.com> wrote in message
news:fOXHd.15$ML4.350@news-west.eli.net...

> Since your synthesis shows 15 LUTs used, I expect that the sum is the
> cascade of 2 9-bit adders.

... sorry: Two 8-bit adders with 9-bit results.

Thanks.

And how much does Synplify cost?

An answer not posted to the group:

Macros are not components that can be instantiated in HDL.  Macros are
only available in ECS, the Xilinx schematic entry tool.

One way to see how Xilinx implements the ADD8 macros is to create the
macro using ECS and then looking at the HDL output of ECS (*.VHF file
generated after synthesis).

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message
news:10v27avp1mno13b@corp.supernews.com...
> Thanks.
>
> And how much does Synplify cost?

Their sales folks will be happy to talk to you.

http://www.synplicity.com/corporate/globallocations/index.html

Be sure to consider the Synplify or Synplify Pro product with HDL Analyst -
an add-on.

While I use Synplify (non-pro) there are benefits with retiming and
auto-constraints for aggressive performance in the Pro product worth
considering since so much time is spent trying to eke out that last
nanosecond in some paths.

Brad Smallridge wrote:
> An answer not posted to the group:
> 
> Macros are not components that can be instantiated in HDL.  Macros are
> only available in ECS, the Xilinx schematic entry tool.

In the XACT days there were ways of doing this.  You make an
empty HDL module with the appropriate I/Os, and if you want
to simulate it you can include non-synthesizable code.

At some point after synthesis and before place and route you 
tell it to remove the dummy and substitute the macro version 
instead.

It might be that a similar method is available with current tools.

-- glen