How to get 1.8432 MHz out of 24 MHz with Sparten-3?

Hello

I'm using a Spartan-3. I'm wondering if there is an easy way to
fabricate a clock with 1.8432 MHz from a 24 MHz input clock?

Could I use a DCM to get this exact clock frequency?

Or should I make a frequency that over a period of time has an average
of 1.8432 MHz?

On 22 Jan 2005 10:38:45 -0800, skolpojken72@yahoo.se (Elektro) wrote:

>Hello
>
>I'm using a Spartan-3. I'm wondering if there is an easy way to
>fabricate a clock with 1.8432 MHz from a 24 MHz input clock?
>
>Could I use a DCM to get this exact clock frequency?
>
>Or should I make a frequency that over a period of time has an average
>of 1.8432 MHz?

Is divide by 13 not close enough...? 1.8461 would be close enough for RS232 comms

Elektro wrote:

> Hello
> 
> I'm using a Spartan-3. I'm wondering if there is an easy way to
> fabricate a clock with 1.8432 MHz from a 24 MHz input clock?
> 
> Could I use a DCM to get this exact clock frequency?
> 
> Or should I make a frequency that over a period of time has an average
> of 1.8432 MHz?
The answer is that you don't need 1.8432MHz. I assume you use that clock
speed for your UART. Just adjust the register of divider in your UART,
and it should be able to run with other clock speeds that can be easily
derived from the 24MHz crystal.

vax, 9000

"Mike Harrison" <mike@whitewing.co.uk> wrote in message 
news:jke5v0h4o2vfurfsv9allhdo8ir9cm3g0n@4ax.com...
> On 22 Jan 2005 10:38:45 -0800, skolpojken72@yahoo.se (Elektro) wrote:
>
>>Hello
>>
>>I'm using a Spartan-3. I'm wondering if there is an easy way to
>>fabricate a clock with 1.8432 MHz from a 24 MHz input clock?
>>
>>Could I use a DCM to get this exact clock frequency?
>>
>>Or should I make a frequency that over a period of time has an average
>>of 1.8432 MHz?
>
> Is divide by 13 not close enough...? 1.8461 would be close enough for 
> RS232 comms

240000 / 18432 = 625 / 48

How about a 10-bit register that decrements by 48 every clock tick.
Whenever it goes negative, add 625 as well and output a UART clock pulse.
Alternatively, if the last clock tick sent it negative, add (625-48)= 577 on 
the next.

I think this should give the exact average frequency, with a little jitter 
(edges may vary by one 24MHz clock period.

I'm not using it for an UART. It's used for an ADS1251 AD-converter to get
an exact sampling frequency of 4800 Hz.

But now I got some new ideas, thanks :-)

"Kryten" <kryten_droid_obfusticator@ntlworld.com> skrev i meddelandet
news:EpzId.1975$uK5.52@newsfe3-gui.ntli.net...
>
> "Mike Harrison" <mike@whitewing.co.uk> wrote in message
> news:jke5v0h4o2vfurfsv9allhdo8ir9cm3g0n@4ax.com...
> > On 22 Jan 2005 10:38:45 -0800, skolpojken72@yahoo.se (Elektro) wrote:
> >
> >>Hello
> >>
> >>I'm using a Spartan-3. I'm wondering if there is an easy way to
> >>fabricate a clock with 1.8432 MHz from a 24 MHz input clock?
> >>
> >>Could I use a DCM to get this exact clock frequency?
> >>
> >>Or should I make a frequency that over a period of time has an average
> >>of 1.8432 MHz?
> >
> > Is divide by 13 not close enough...? 1.8461 would be close enough for
> > RS232 comms
>
> 240000 / 18432 = 625 / 48
>
> How about a 10-bit register that decrements by 48 every clock tick.
> Whenever it goes negative, add 625 as well and output a UART clock pulse.
> Alternatively, if the last clock tick sent it negative, add (625-48)= 577
on
> the next.
>
> I think this should give the exact average frequency, with a little jitter
> (edges may vary by one 24MHz clock period.
>
>
>
>
>
>
>

>I'm not using it for an UART. It's used for an ADS1251 AD-converter to get
>an exact sampling frequency of 4800 Hz.

What do you mean by "exact"?  How good is the crystal you are
starting with?

24 MHz divided by 5000 gives a nice clean 4800 HZ.
Why go through 1.8432 MHz?

Another way to look at things...
  To go from 1.8432 to 4800 Hz, you divide by 384
  To go from 24 MHz to 4800 Hz, you divide by 5000
  The factors of 384 are: 2 2 2 2 2 2 2 3
  The factors of 5000 are: 2 2 2 5 5 5 5
You are going to have troubles going through 1.8432
on the way from 24 MHz to 4800 Hz.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
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Hal Murray wrote:

>>I'm not using it for an UART. It's used for an ADS1251 AD-converter to get
>>an exact sampling frequency of 4800 Hz.
> 
> 
> What do you mean by "exact"?  How good is the crystal you are
> starting with?
> 
> 24 MHz divided by 5000 gives a nice clean 4800 HZ.
> Why go through 1.8432 MHz?

I'd guess the ADS1251 starts with that ?

So there are a couple of choices

a) Divide by 13, and accept the slight sample error, but zero jitter,
or
b) divide by 625/48 as someone else suggested.

However, rather than implement split adders as counters, this can also 
be done with a much simpler swallow counter :

for 47/48 times divide by 13, and for 1/48 times, divide by 14.

Result is 625 clocks in, for 48 out.
Freq average is exact, but has slight edge jitter on the /14 cases

-jg

On Mon, 24 Jan 2005 17:49:18 +1300, Jim Granville
<no.spam@designtools.co.nz> wrote:

>
>
>Hal Murray wrote:
>
>>>I'm not using it for an UART. It's used for an ADS1251 AD-converter to get
>>>an exact sampling frequency of 4800 Hz.
>> 
>> 
>> What do you mean by "exact"?  How good is the crystal you are
>> starting with?
>> 
>> 24 MHz divided by 5000 gives a nice clean 4800 HZ.
>> Why go through 1.8432 MHz?
>
>I'd guess the ADS1251 starts with that ?
>
>So there are a couple of choices
>
>a) Divide by 13, and accept the slight sample error, but zero jitter,
>or
>b) divide by 625/48 as someone else suggested.
>
>However, rather than implement split adders as counters, this can also 
>be done with a much simpler swallow counter :
>
>for 47/48 times divide by 13, and for 1/48 times, divide by 14.
>
>Result is 625 clocks in, for 48 out.
>Freq average is exact, but has slight edge jitter on the /14 cases

... even simpler to use a script that writes the HDL for you.  (This
way, there is no chance of making an error.)

http://fractional-divider.tripod.com/

BTW, "slight edge jitter" is 41ns p-p.

Regards,
Allan

Thank you all. I made a 625/96 divider and toggled the clock output bit by
that, and it worked nicely. :-) I got 48 clocks out when I put 625 clocks
in.



Others than me selected this "odd" frequency, so I couldn't select a more
appropriate one by myself. :-/ Otherwise I would have selected another
frequency.





And by the way, does anybody know a good book with these kinds of examples?





Thanks :-)


"Jim Granville" <no.spam@designtools.co.nz> skrev i meddelandet
news:41f47e00$1@clear.net.nz...
>
>
> Hal Murray wrote:
>
> >>I'm not using it for an UART. It's used for an ADS1251 AD-converter to
get
> >>an exact sampling frequency of 4800 Hz.
> >
> >
> > What do you mean by "exact"?  How good is the crystal you are
> > starting with?
> >
> > 24 MHz divided by 5000 gives a nice clean 4800 HZ.
> > Why go through 1.8432 MHz?
>
> I'd guess the ADS1251 starts with that ?
>
> So there are a couple of choices
>
> a) Divide by 13, and accept the slight sample error, but zero jitter,
> or
> b) divide by 625/48 as someone else suggested.
>
> However, rather than implement split adders as counters, this can also
> be done with a much simpler swallow counter :
>
> for 47/48 times divide by 13, and for 1/48 times, divide by 14.
>
> Result is 625 clocks in, for 48 out.
> Freq average is exact, but has slight edge jitter on the /14 cases
>
> -jg
>

On Mon, 24 Jan 2005 16:17:57 +0100, "Elektro" <mrs@telia.com> wrote:

>Thank you all. I made a 625/96 divider and toggled the clock output bit by
>that, and it worked nicely. :-) I got 48 clocks out when I put 625 clocks
>in.

Are you aware of the effects of clock jitter on ADC performance?  You
should check with your system designers about this effect, otherwise
you may get "sub-optimal" results, i.e. it won't work.

The ADS1251 is a 24 bit ADC.
Assuming a full scale input signal of 1000Hz (a guess, based on Fs =
4800Hz), 41ns p-p of clock jitter will degrade the performance to
about 12 bits.
This gets better as the input frequency is reduced, e.g. a 100Hz input
will give about 15-16 bits.
(I made some assumptions that may not apply to Sigma-Delta ADCs
though.  Unfortunately, the ADS1251 data sheet does not mention its
sensitivity to jitter.)


It's possible that the divide by 13 counter would be better, as it
generates no jitter.  Can you tolerate the frequency error?

Regards,
Allan