60Hz clock on XC9572

I've been trying to divide a 60Hz signal down to 1Hz and slower using
an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60,
and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input
which seemed to remove some problems. It still has random delays in the
output.  Is 60Hz too slow for this device?

Nathan

nathan_wilson@hotmail.com wrote:
> I've been trying to divide a 60Hz signal down to 1Hz and slower using
> an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60,
> and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input
> which seemed to remove some problems. It still has random delays in the
> output.  Is 60Hz too slow for this device?

An RF choke sounds good, but you should have more than that.

A Schmidt trigger so it doesn't count noise that still comes 
through.    Otherwise 60Hz counting isn't too slow, but the
edge must be faster than that.  If you put it through a few
inverters (and make sure they don't get optimized away) that
would speed up the transition.

-- glen

<nathan_wilson@hotmail.com> wrote in message 
news:1106590027.557745.170670@f14g2000cwb.googlegroups.com...
> I've been trying to divide a 60Hz signal down to 1Hz and slower using
> an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60,
> and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input
> which seemed to remove some problems. It still has random delays in the
> output.  Is 60Hz too slow for this device?
>
> Nathan

You need a good sharp edge transition.  Buffer the signal with a 
schmidtt-trigger, something along the lines of a 74HC14 should work.  Tie 
the HC14's unused inputs to a single level so they don't make the unused 
output chatter.

I'm assuming you have already done some kind of signal conditioning on the 
60Hz signal to make it at least TTL compatible.

Rob Young

nathan_wilson@hotmail.com wrote:
> I've been trying to divide a 60Hz signal down to 1Hz and slower using
> an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60,
> and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input
> which seemed to remove some problems. It still has random delays in the
> output.  Is 60Hz too slow for this device?

A 60Hz sine wave certainly is.
Where does the 60Hz come from - i guess the AC mains
[hopefully isolated]?

  You will need a low pass filter, and a schmitt trigger, to give
the fast clock edges the PLD likes.
The low pass filter can be series R with shunt C, and should
have a corner < 100Hz.
  There is a lot of glitch noise on the AC mains, and the 9572 will 
otherwise faithfully count those that fall inside the schmitt crossing 
band. The LPF removes that.
-jg

<nathan_wilson@hotmail.com> wrote in message
news:1106590027.557745.170670@f14g2000cwb.googlegroups.com...
> I've been trying to divide a 60Hz signal down to 1Hz and slower using
> an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60,
> and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input
> which seemed to remove some problems. It still has random delays in the
> output.  Is 60Hz too slow for this device?
>
> Nathan
>

What else do you have in the pld?  A "normal" clk?  some extra ff's?  I
would set  ff Q1  when 60 hz = '1' and QUAL = '0' and clear ff Q1 when 60 hz
= '0' and QUAL = '1' where QUAL is ff Q1 delayed by a ms or so using the
"normal" clk and some ff's.  Use ff Q1 as your 60 hz global clk and you
should be good to go.  If you do this you can probably lose the rf choke
too.

Dan,
Yep, this is what I do for clipped sine-wave TCXOs on my Xilinx FPGAs. I use
the input delay in spare unbonded IOBs for the delay. Works a treat, and no
Schmitts required!
Cheers, Syms.
"Dan K" <danielgkNOSPAM@voomtech.com> wrote in message
news:41f57d5c$0$2164$a1866201@visi.com...
>
> What else do you have in the pld?  A "normal" clk?  some extra ff's?  I
> would set  ff Q1  when 60 hz = '1' and QUAL = '0' and clear ff Q1 when 60
hz
> = '0' and QUAL = '1' where QUAL is ff Q1 delayed by a ms or so using the
> "normal" clk and some ff's.  Use ff Q1 as your 60 hz global clk and you
> should be good to go.  If you do this you can probably lose the rf choke
> too.
>

Low-pass filter followed by Schmitt trigger is the only safe bet.
Here is the simplest Schmitt tigger:
Inside the chip, route the incoming signal non-inverted to an other
pin, as output.
Run a 10 kilohm resistor from that output to the input. (Yes, I know,
that forms a latch) Now drive the input from your low-impedance 60 Hz
source through a 1 kilohm resistor.
This gives you 10% of Vcc as hysteresis. For different values, play
with the two resistor valus.

Costs one extra pin and two resistors, saves lots of headaches.
Peter Alfke, Xilinx Applications

Peter Alfke wrote:
> Low-pass filter followed by Schmitt trigger is the only safe bet.
> Here is the simplest Schmitt tigger:
> Inside the chip, route the incoming signal non-inverted to an other
> pin, as output.
> Run a 10 kilohm resistor from that output to the input. (Yes, I know,
> that forms a latch) Now drive the input from your low-impedance 60 Hz
> source through a 1 kilohm resistor.
> This gives you 10% of Vcc as hysteresis. For different values, play
> with the two resistor valus.
> 
> Costs one extra pin and two resistors, saves lots of headaches.
> Peter Alfke, Xilinx Applications

or use a PLD with Hysteresis inbuilt ?
or, for the low impedance buffer you mention, choose a
single gate device like 1G14/1G17 ?

If power consumption mattered, the above R-R schmitt is sub optimal,
but I guess with a 9572 who cares...

-jg

"Peter Alfke" <alfke@sbcglobal.net> wrote in message
news:1106626400.522496.188140@f14g2000cwb.googlegroups.com...
> Low-pass filter followed by Schmitt trigger is the only safe bet.
Pedantically, I disagree. Debouncing with delays is also a safe bet. It can
also saves all those R's & C's! See Dan's post.
Cheers, Syms.

Pedantically you are right.
Practically, three resistors and a capacitor are better.
Peter Alfke