Xilinx Engineering Samples

I've got several boards from Memec-Insight with the Virtex 4 LX-25.
Unfortunately they are marked "Engineering Samples", which worries
me.

Can some one from Xilinx explain the difference between Engineering
Samples and Production devices ? Are there any function/electrical/
timing differences ?

Thanks,
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

Rudolf Usselmann wrote:

> 
> I've got several boards from Memec-Insight with the Virtex 4 LX-25.
> Unfortunately they are marked "Engineering Samples", which worries
> me.
> 
> Can some one from Xilinx explain the difference between Engineering
> Samples and Production devices ? Are there any function/electrical/
> timing differences ?
> 
> Thanks,
> rudi
> =============================================================
> Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
> Your Partner for IP Cores, Design, Verification and Synthesis

Rudi,

You must download the XC4VLX25CES errata datasheet, find out what the
short comings are, and decide if they matter for your application and 
evaluation. Unfortunately, the Xilinx web site uses session specific dynamic 
links, so this is as close as I can get an exact url to point you to the pdf 
for the ES. Go to the errata section at the bottom of this page:
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Virtex-4&iLanguageID=1

This datasheet describes some JTAG specific issues that may be the root
cause of your other post.  More power requirements during init -- check 
your power supplies!

Thanks, Steve

Let me give a more generic answer about ES.
"Engineering Samples" is really an inappropriate name, I would call it
"Early Silicon"  :-)
The devices are thoroughly tested and perform according to the data
sheet, as amended by an errate sheet. By definition, ES parts have an
errate sheet (at best it says:"NO ERRATA")
We call them ES because some long-term reliability qualification tests
have not yet been completed. We might also have to change some masks to
fix the errata problem(s).
We therefore suggest that ES parts not be used in your final
manufacturing.
But any idea that ES parts are flakey, not completely tested, or
unreliable is dead WRONG.
Hope that helps.
Peter Alfke, Xilinx Applications

Peter Alfke wrote:
> We call them ES because some long-term reliability qualification tests
> have not yet been completed.

And a little later...

> But any idea that ES parts are flakey, not completely tested, or
> unreliable is dead WRONG.

Hmm...

First you say that "some" ... tests have not yet been completed, and
then you say "not completely tested ... is dead WRONG".  I hate to
quibble, but you ain't having it both ways...  :-)

-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Tobias,

There is a goal that we must reach to call the product 'production' in 
terms of test coverage.

So, let us say that ES might be 99.997% covered, but the goal is 99.998% 
(these are not the actual numbers, but are representative of the 
differences we are talking about).

Austin

Tobias Weingartner wrote:

> Peter Alfke wrote:
> 
>>We call them ES because some long-term reliability qualification tests
>>have not yet been completed.
> 
> 
> And a little later...
> 
> 
>>But any idea that ES parts are flakey, not completely tested, or
>>unreliable is dead WRONG.
> 
> 
> Hmm...
> 
> First you say that "some" ... tests have not yet been completed, and
> then you say "not completely tested ... is dead WRONG".  I hate to
> quibble, but you ain't having it both ways...  :-)
> 

Tobias, let me assume you are serious:
I wrote that some reliability qualification test have not been
completed.
But I also said that the parts are completely tested.

Anybody familiar with IC testing understands that.
The production testing is done 100% (functionality plus ac and dc
parameters)
The reliability qualification test are something completely different.
The word "test" has several meanings.
Now, if you are a lawyer...
Peter
=====================
Tobias Weingartner wrote:
> Peter Alfke wrote:
> > We call them ES because some long-term reliability qualification
tests
> > have not yet been completed.
>
> And a little later...
>
> > But any idea that ES parts are flakey, not completely tested, or
> > unreliable is dead WRONG.
>
> Hmm...
>
> First you say that "some" ... tests have not yet been completed, and
> then you say "not completely tested ... is dead WRONG".  I hate to
> quibble, but you ain't having it both ways...  :-)
>
> --
>
[100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Steve wrote:

> Rudolf Usselmann wrote:
> 
>> 
>> I've got several boards from Memec-Insight with the Virtex 4 LX-25.
>> Unfortunately they are marked "Engineering Samples", which worries
>> me.
>> 
>> Can some one from Xilinx explain the difference between Engineering
>> Samples and Production devices ? Are there any function/electrical/
>> timing differences ?
>> 
>> Thanks,
>> rudi
>> =============================================================
>> Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
>> Your Partner for IP Cores, Design, Verification and Synthesis
> 
> Rudi,
> 
> You must download the XC4VLX25CES errata datasheet, find out what the
> short comings are, and decide if they matter for your application and
> evaluation. Unfortunately, the Xilinx web site uses session specific
> dynamic links, so this is as close as I can get an exact url to point you
> to the pdf for the ES. Go to the errata section at the bottom of this
> page:
>
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Virtex-4&iLanguageID=1
> 
> This datasheet describes some JTAG specific issues that may be the root
> cause of your other post.  More power requirements during init -- check
> your power supplies!
> 
> Thanks, Steve

What is the likelihood that the "errors" in the errata will be
fixed for the production devices for the V4LX25 ?

rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

Peter Alfke wrote:

> Let me give a more generic answer about ES.
> "Engineering Samples" is really an inappropriate name, I would call it
> "Early Silicon"  :-)
> The devices are thoroughly tested and perform according to the data
> sheet, as amended by an errate sheet. By definition, ES parts have an
> errate sheet (at best it says:"NO ERRATA")
> We call them ES because some long-term reliability qualification tests
> have not yet been completed. We might also have to change some masks to
> fix the errata problem(s).
> We therefore suggest that ES parts not be used in your final
> manufacturing.
> But any idea that ES parts are flakey, not completely tested, or
> unreliable is dead WRONG.
> Hope that helps.
> Peter Alfke, Xilinx Applications

Peter,

According to the errata there seem to be some serious
problems with some of the ES parts. I would assume Xilinx
would strive to fix those ? Or am I wrong ?

Regards,
rudi
=============================================================
Rudolf Usselmann,  ASICS World Services,  http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis

Peter Alfke wrote:

> Now, if you are a lawyer...

Then I would not care at all and just make something up ;-)

Kolja Sulimma

Rudolf Usselmann wrote:

> Steve wrote:
> 
>> Rudolf Usselmann wrote:
>> 
>>> 
>>> I've got several boards from Memec-Insight with the Virtex 4 LX-25.
>>> Unfortunately they are marked "Engineering Samples", which worries
>>> me.
>>> 
<SNIP> 
> This datasheet describes some JTAG specific issues that may be the root
> cause of your other post.  More power requirements during init -- check
> your power supplies!
> 
<SNIP>

> What is the likelihood that the "errors" in the errata will be
> fixed for the production devices for the V4LX25 ?
> 
> rudi

Rudi,
	I have no association with Xilinx, so I suggest you
develop a contact with Xilinx to get a real answer.  Getting the 
inside "what and when" story on fixes is unlikely to be revealed
in this forum, due to what should be obvious competitive reasons.

	In all fairness, Engineering Samples are early version
product that many manufacturers ship to get something in the hands
of their customers so that they can hopefully get a major portion of
a design debugged before the final product is available. I've been glad
to get ES parts, given the alternative of waiting. Typically the errata
is corrected in the final product, but there is no guarantee. My 
experience with ES parts has been that the issues can be worked around 
or put off, so that I can complete >90% of my design with the ES parts.
However, if one of the errata issues is critical to your application, 
you are screwed.  Maybe I've been lucky.  YMMV, buyer beware, do your
home work.

	The errata datasheet seems to suggest a higher initialization 
current draw with this ES part, though I may be jumping to conclusions, 
since I've _not_ even looked at this part's full datasheet.  (I've personally
seen higher current draw for ES parts during init with a competing FPGA 
manufacturer who's name begins with "A," so it is my knee jerk reaction.)
It is certainly an easy check for you to confirm that you are not 
experiencing some sort of power supply glitch during init.  Instability 
would not be unheard of if LDO regulators are being used, for example.

Good Luck, Steve