Synchronous counter enable pulse length

"Vinh Pham" <vinh-pham@hawaii.rr.com> wrote in message
news:tUkcb.1068$5z.548@twister.socal.rr.com...
> > It was more obvious to me connecting Qbar to D of the same FF.  Then
there
> > is no question about clock skew.
>
> That's a good idea too.  Whatever works for you.
>
> > But if there is clock skew, then even zero hold time isn't
> > good enough. You can't make it too easy.
>
> I was simplifying the example for the sake of making things easier to
> understand.  But you are correct that during real design you need to take
> clock skew into account.  That is one reason why FPGA vendors make great
> efforts to provide a low skew clock network.  I'm sure FPGA software also
> takes clock skew into account when analyzing a design.
>
> >Not so long ago I was reading about the design of pipelined computers.
> >In most cases there should be enough logic never to have to
> > worry about hold time, but in some cases FF's are wired with no logic
> > in between.  Then you might need to add some to be sure.
>
> Yeah I agree with you that there's usually enough logic so you wouldn't
have
> to worry.  And with FPGAs a significant amount of delay comes from the
> routing.
>
> One advantage of having zero hold-time parts is that you can port a proven
> design to a faster speed grade without having to worry about a hold-time
> violation.

I think this is what Peter was trying to point out somewhere along the line.

> >There is also a design for a combination latch and two level of logic.
> >That helps in allowing faster clocks for the
> > amount of logic per pipeline stage.
>
> Do you happen to have a URL to that example?  It sounds interesting.

It is called the "Earle latch", which seems to find 38 hits on Google.

I have no idea if it is at all useful today.  Consider that it was in the
days when individual transistors were glued onto ceramic chips, with
metalized wiring on them.   The 360/91 was built with pretty much a discrete
version of ECL.

The book I have is called "The Architecture of Pipelined Computers" by Peter
M. Kogge.  Copyright 1981, so you might consider it more of a history book.
Still, many ideas from that time are still in use today.

-- glen

> Still, many ideas from that time are still in use today.

That is true.  And sometimes people discover new uses for old techniques.
It never hurts to learn them, because they can give you ideas on how to
solve your current problems.  Thanks for the information Glen.  I found a
lot of links to Earle Latches but no diagrams.  I guess the design is too
old for the internet.


--v

"Vinh Pham" <a@a.a> wrote in message
news:r7ncb.1311$5z.1162@twister.socal.rr.com...
> > Still, many ideas from that time are still in use today.
>
> That is true.  And sometimes people discover new uses for old techniques.
> It never hurts to learn them, because they can give you ideas on how to
> solve your current problems.  Thanks for the information Glen.  I found a
> lot of links to Earle Latches but no diagrams.  I guess the design is too
> old for the internet.

I wonder if I can get this to work:


Fixed width font required:

clock -------
             | nand )------------\
data --------                     \
        |                          \
        |----
             | nand )---------------| nand ) -------------- out
     out ----
          |                        /
         ----                     /
             | nand )------------/
clockbar ----


Clock and its inverse, clockbar, apparently don't have so strict timing
requirements as one might guess.

To implement AND/OR logic, the number of inputs on the final nand can
be increased, and additional copies of the left middle nand can be
added, also with more inputs.

-- glen

Peter Alfke <peter@xilinx.com> wrote in message news:<3F6F9240.E1B74AB5@xilinx.com>...
> Here are some practical points.
> For all but the most extremely fast applications ( say up to 200 MHz),
> synchronous counters are built using a global clock, and the bult-in
> free ripple carry structure, which of course determines a max frequency
> (where the ripple carry can still meet the set-up time requirements of
> the MSB.) Decoding TC can be quite tricky, that's why I suggested the
> digital differentiator which actually detects TC+1.

It is interesting to see this discussion come up, I had never thought 
about doing a cout/TC (delayed) in this way!

To implement the "digital differentiator", the best I could come up with 
was a falling edge detector on MSB using an AND gate, an inverter and a 
flip-flop.

D gets the MSB and Q is ANDed with NOT(MSB). Depending on use, I guess 
the AND output could be synchronized (delay of 2 clocks then) if needed.

Keeping this clever TC method in mind, I'm trying to build a 
programmable frequency divider which uses a 20-bit loadable synchronous 
counter. The divisor is held in a register and is arbitrary, so no 
clever apriori optimizations. Currently I'm targetting a Flex6K but I'm 
also eyeing a Xilinx Spartan XL part.

I found if I have a counter setup to count down and decode on count == 1 
which drives a DFF and is used to SLOAD the counter, I need a large 
number of LUTs to implement the decode/compare logic(not surprising).

To use the TC method above(counting-up), I need to load my counter with 
the 1's complement of my divisor.

Is the only alternative to count-down (and lots of LUTs) or count-up/TC 
(1's comp. of divisor) for my frequency generator to use a phase 
accumulator arrangement? Did I miss any other clever tricks?

Thanks in advance.

-- Jay