After over 2 years of waiting Actel has finally announced ProAsic3 Flash-FPGAs with lowest price tag starting 1.5USD They also claim Libero 6.1 supports ProASIC3 Well when I tried Libero 6.1 then it did not work for any selectable PA3 device - and here is reply from Actal, quote "Hi Antti, The programming file generation is disable in this version. Since, you don't have any sample part and this option is not available." So because they (Actel) KNOW that I (Antti) do not have PA3 samples it means it is OK to ship Libero without support of programming file generation and still claim it supports PA3, because I the poor soul would not have any silicon to test with anyway? I probably wanted to see if my STAPL player is compatible with the PA3 programming file generated, and for that purpose I dont need silicon, but need a programming file, right? [auto-censored stuff deleted...] Antti Lukats
ProASIC=?ISO-8859-1?Q?=A7?= Released
Started by ●January 27, 2005
Reply by ●January 27, 20052005-01-27
Antti Lukats wrote:> After over 2 years of waiting Actel has finally announced ProAsic3 Flash-FPGAs with lowest price tag starting 1.5USD > > They also claim Libero 6.1 supports ProASIC3 > > Well when I tried Libero 6.1 then it did not work for any selectable PA3 device - and here is reply from Actal, quote > > "Hi Antti, The programming file generation is disable in this version. Since, you don't have any sample part and this option is not available." > > So because they (Actel) KNOW that I (Antti) do not have PA3 samples it means it is OK to ship Libero without support of programming file generation and still claim it supports PA3, because I the poor soul would not have any silicon to test with anyway? > > I probably wanted to see if my STAPL player is compatible with the PA3 programming file generated, and for that purpose I dont need silicon, but need a programming file, right? > > [auto-censored stuff deleted...]:) If that was a genuine excuse, you have a right to feel miffed, but probably the real reason is that the Software is so much in Beta mode, that it hardly completes a task, and they are franticaly trying to sort it.... The above buys them time, without admiting problems. Still, I'd imagine your stapl player would tolerate synthesis bugs in the programming file, so you could go back, and ask them to enable it, and you will promise not to send the results to a real chip.... ? :) -jg
Reply by ●January 27, 20052005-01-27
Antti Lukats wrote:> After over 2 years of waiting Actel has finally announced ProAsic3 Flash-FPGAs with lowest price tag starting 1.5USD > > They also claim Libero 6.1 supports ProASIC3 > > Well when I tried Libero 6.1 then it did not work for any selectable PA3 device - and here is reply from Actal, quote > > "Hi Antti, The programming file generation is disable in this version. Since, you don't have any sample part and this option is not available."<snip> Keep us posted with progress.... These do look like nice devices, remind me of MAX II, but _WITH_ SRAM, which was the glaring oops in MAX II.... Lattice have a FLASH FPGA solution comming as well, 2005 looks to be an interesting year... -jg
Reply by ●January 27, 20052005-01-27
Hi Jim, any more about this lattice info I mean of what you can say ;) I have a bit more about PA3, there: <http://www.openchip.org/mambo/index.php?option=com_content&task=view&id=12&Itemid=1> the OOPS with PA3 is that the blockRAM can not be used as ROM, no init from config, and that the FROM (1k flash array) is not writeable from FPGA only from ext JTAG and MAX2 has no BlockRAM, so interesting what the Lattice thing will be, and what OOPses are there Antti
Reply by ●January 27, 20052005-01-27
Antti Lukats wrote:> Hi Jim, > > any more about this lattice info I mean of what you can say ;)Hi Antti, Well, this was the info released on Sept 10th : "In addition, Lattice has recently received the first 130nm Flash-based products and the first 90nm products fabricated by Fujitsu, which are currently in the early stages of evaluation." These are the ones comming after the already released EC/ECP FPGAs. Actel say Q4 for production, so there is time for Lattice to come to the party. Some vendors have long vapor-ware times, and some do not. eg TI came onto the ARM uC scene with merchant TMS470's quite quickly.> I have a bit more about PA3, there: > > <http://www.openchip.org/mambo/index.php?option=com_content&task=view&id=12&Itemid=1> > > the OOPS with PA3 is that the blockRAM can not be used as ROM, no init from configand no serial load, you have to consume FPGA fabric to init...> and that the FROM (1k flash array) is not writeable from FPGA only from ext JTAGthat's somewhat understandable. Still, 1K is probably (just) enough to include a tiny-boot-load, so a MUX is not needed in the critical RAM path of a SoftCPU.> > and MAX2 has no BlockRAM, so interesting what the Lattice thing will be, and what OOPses are thereIcc and esp the Vcc range specs of PA3 look nice. ie They admit it operates at low Vcc, just not at full speed. Potential for ideas there, but no Icc/Vcc plots yet... The "F" grade is also an interesting idea - looks a bit like the yield failures, in Tpd and Icc, and some apps are really don't care on speed or Icc, so it allows them to ship low price devices. ( hopefully the $1.50 price is not for 'F' grade.. :) ) Nice low Min Freqs on the PLLs too... Good package ranges, but why only the smallest in MLF132 ? ( die too large on the others ? ) -jg
Reply by ●January 27, 20052005-01-27
Antti Lukats wrote:> Hi Jim, > > any more about this lattice info I mean of what you can say ;) > > I have a bit more about PA3, there: > > <http://www.openchip.org/mambo/index.php?option=com_content&task=view&id=12&Itemid=1> > > the OOPS with PA3 is that the blockRAM can not be used as ROM, no init from config, and that the FROM (1k flash array) is not writeable from FPGA only from ext JTAG > > and MAX2 has no BlockRAM, so interesting what the Lattice thing will be, and what OOPses are there > > AnttiThey are called XP devices...looks like EC with integrated flash memory for configuration...have some presentation around which I received last November.. rick
Reply by ●January 27, 20052005-01-27
ispXPGA? those are "old" stuff it was available long time before EC/ECP was announced, I did think jg was referring something new, eg not-announced lattice product... antti
Reply by ●January 28, 20052005-01-28
No, no, It is called XP, based on 130nm flash tech from fujitsu. Performance-wise like the EC,and non-volatile like the ispXPGA. But this was E�, and therefore a lot more expensive. You can expect the XP in the price range of the EC. Regards, Luc On Thu, 27 Jan 2005 11:09:52 -0800, "Antti Lukats" <antti@openchip.org> wrote:>ispXPGA? those are "old" stuff it was available long time before EC/ECP was announced, I did think jg was referring something new, eg not-announced lattice product... > >antti
Reply by ●January 28, 20052005-01-28
Luc wrote:> No, no, > > It is called XP, based on 130nm flash tech from fujitsu. > Performance-wise like the EC,and non-volatile like the ispXPGA. But > this was E�, and therefore a lot more expensive. You can expect the XP > in the price range of the EC.Actually price range will be EC + external SPI flash (o; rick> > Regards, > > Luc > > On Thu, 27 Jan 2005 11:09:52 -0800, "Antti Lukats" > <antti@openchip.org> wrote: > > >>ispXPGA? those are "old" stuff it was available long time before EC/ECP was announced, I did think jg was referring something new, eg not-announced lattice product... >> >>antti > >
Reply by ●January 31, 20052005-01-31
Jedi wrote:> Luc wrote: > >> No, no, >> >> It is called XP, based on 130nm flash tech from fujitsu. >> Performance-wise like the EC,and non-volatile like the ispXPGA. But >> this was E�, and therefore a lot more expensive. You can expect the XP >> in the price range of the EC. > > > Actually price range will be EC + external SPI flash (o; > > > rick > > >> >> Regards, >> >> Luc >> >> On Thu, 27 Jan 2005 11:09:52 -0800, "Antti Lukats" >> <antti@openchip.org> wrote: >> >> >>> ispXPGA? those are "old" stuff it was available long time before >>> EC/ECP was announced, I did think jg was referring something new, eg >>> not-announced lattice product... >>> >>> antti >> >> >>I think that the XP replaces the "DSP blocks" in the ECP device with flash (EEPROM) memory blocks for storing the configuration bits. Ben
