If you click on http://seminar2.techonline.com/s/xilinx_feb0105 and register for the Feb.1 Xilinx TechOnLine, then you can witness my presentation about Virtex-4 performance. It's a daring high-wire act between engineering and marketing. Wish me luck! The time is Tuesday, Feb 1, noon to 1 pm Pacific time. It would be nice to feel that I can count on some friends in the invisible audience. Peter Alfke, Xilinx Applications
See Peter's High-Wire Act next Tuesday
Started by ●January 27, 2005
Reply by ●January 27, 20052005-01-27
"Peter Alfke" <peter@xilinx.com> wrote in message news:1106877046.479990.51180@z14g2000cwz.googlegroups.com...> > > If you click on > > http://seminar2.techonline.com/s/xilinx_feb0105 > > and register for the Feb.1 Xilinx TechOnLine, then you can witness my > presentation about Virtex-4 performance. It's a daring high-wire act > between engineering and marketing. Wish me luck! > > The time is Tuesday, Feb 1, noon to 1 pm Pacific time. > It would be nice to feel that I can count on some friends in the > invisible audience. > > Peter Alfke, Xilinx Applications >Peter, Thanks for the heads-up. You'll do great. And remember, we'll all be sitting behind our monitors -- NAKED!!! Thinking about this fact should relieve any potential nervousness you will have. Bob
Reply by ●January 31, 20052005-01-31
Don't forget, it's tomorrow, Tuesday, at noon Pacific Time. Altera Marketing has e-mailed me and promised their attendance. I will not disappoint them. So join me tomorrow for some serious and fun talk on FPGA performance. Peter> "Peter Alfke" <peter@xilinx.com> wrote in message > news:1106877046.479990.51180@z14g2000cwz.googlegroups.com... > > > > > > If you click on > > > > http://seminar2.techonline.com/s/xilinx_feb0105 > > > > and register for the Feb.1 Xilinx TechOnLine, then you can witnessmy> > presentation about Virtex-4 performance. It's a daring high-wireact> > between engineering and marketing. Wish me luck! > > > > The time is Tuesday, Feb 1, noon to 1 pm Pacific time. > > It would be nice to feel that I can count on some friends in the > > invisible audience. > > > > Peter Alfke, Xilinx Applications > > > >
Reply by ●February 2, 20052005-02-02
Peter, You were superb! Those built-in async fifo controllers, in Virtex-4, are amazing. I wasn't aware that they were in there. It's a good thing that Xilinx had the foresight to hire that FIFO expert (whoever he might be). ;-> Bob "Peter Alfke" <peter@xilinx.com> wrote in message news:1106877046.479990.51180@z14g2000cwz.googlegroups.com...> > > If you click on > > http://seminar2.techonline.com/s/xilinx_feb0105 > > and register for the Feb.1 Xilinx TechOnLine, then you can witness my > presentation about Virtex-4 performance. It's a daring high-wire act > between engineering and marketing. Wish me luck! > > The time is Tuesday, Feb 1, noon to 1 pm Pacific time. > It would be nice to feel that I can count on some friends in the > invisible audience. > > Peter Alfke, Xilinx Applications >
Reply by ●February 2, 20052005-02-02
Thanks, "Bob". There was some confusion about the apparent or virtual delay between slides, and I should perhaps have talked more slowly. But totally I am happy. No responses yet (except yours), but perhaps later. The emotional words about benchmarks were no play-acting. I still have scars from Altera's reckless destruction of the old PREP cooperation, more than a dozen years ago. And they are still up to their same old trickery. Their newest game is giving leakage current values at 25 degrees. Nice numbers, but totally meaningless and utterly misleading. How does one expose this? Legally, it's not exactly a lie, but it has the same effect as if it were. Some engineers and managers may even be inexperienced enough to fall for this kind of nonsense. The question is just: How fast will it backfire? The earlier, the better ! No wonder smart engineers have developed a deep suspicion of marketing... Peter
Reply by ●February 2, 20052005-02-02
Peter Alfke <alfke@sbcglobal.net> wrote:> Thanks, "Bob". > There was some confusion about the apparent or virtual delay between > slides, and I should perhaps have talked more slowly. But totally I am > happy.... Is the recording of the talk available on the net? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply by ●February 2, 20052005-02-02
Peter Alfke wrote:> Thanks, "Bob". > There was some confusion about the apparent or virtual delay between > slides, and I should perhaps have talked more slowly. But totally I am > happy.It was interesting to note that the slides seemed to appear on this side of the pacific, before you were able to see them ?> No responses yet (except yours), but perhaps later. > The emotional words about benchmarks were no play-acting. I still have > scars from Altera's reckless destruction of the old PREP cooperation, > more than a dozen years ago. And they are still up to their same old > trickery.I did think (evil grin) of asking about "Why not use PREP for FPGA benchmarks ? "> Their newest game is giving leakage current values at 25 degrees. Nice > numbers, but totally meaningless and utterly misleading. How does one > expose this? Legally, it's not exactly a lie, but it has the same > effect as if it were. Some engineers and managers may even be > inexperienced enough to fall for this kind of nonsense. The question is > just: How fast will it backfire? The earlier, the better !... Wait for the app notes covering thermal runaway on FPGAs ?> No wonder smart engineers have developed a deep suspicion of > marketing...-jg
Reply by ●February 2, 20052005-02-02
I saw the material and Altera's story as well. Why is Altera talking these unknown design based benchmarks that deal only with the fabric ? I have had more problems meeting I/O bandwidth and timings for 266Mhz I/O designs than anything else.
Reply by ●February 2, 20052005-02-02
Hi Che Fong, Core logic/routing performance is only one aspect of the overall performance/design suitability question. Many customers *do* have trouble meeting timing in the core of their design, and a faster chip (e.g. Stratix II) can make it easier to do so, leaving you with more time/energy to spend on other problems such as I/O interfaces and debugging. A faster chip can also mean you can by a cheaper speed grade and still meet core timing, provided that device meets your other needs. If you don't need core performance at all, then that particular aspect of Stratix II will not be of use to you. Everyone has different needs. Many customers do need speed. Regards, Paul Leventis Altera Corp.
Reply by ●February 2, 20052005-02-02
>Their newest game is giving leakage current values at 25 deg=ADrees.Nice>numbers, but totally meaningless and utterly misleading. How=AD doesone>expose this? Legally, it's not exactly a lie, but it has the=AD same >effect as if it were. Some engineers and managers may even b=ADe >inexperienced enough to fall for this kind of nonsense. The =ADquestionis>just: How fast will it backfire? The earlier, the better !Wow. I can't believe how completely backwards this is -- who is lying here Peter? Who is playing the "games"?>From the very first release in November 2004, all our Stratix II toolshave provided static power as a function of junction temperature (ranging from 25C to 100C) and process (typical and worst-case silicon). Contrast this to your Virtex-4 data. Until two weeks ago, the only available data was 25C, Typical silicon. Then with WPT 4.0 you finally caught up on temperature-dependent static power. But still, only typical silicon. Sub-threshold leakage increases exponentially with threshold voltage and gate length, and thus is extremely sensitive to process variation. I wonder how many of your customers have fallen for your marketing story only to find themselves with atypical units of silicon that burn more power than your spec? Altera prides itself on operational excellence and reliability. This extends to our power models. At the introduction of Stratix II, we provided conservative power specs (both typical and worst-case) to ensure that our customers could safely design to this product. These specs reflected the uncertainty that comes hand-in-hand with software before silicon release. As the various family members have come back from the fab, we have tightened the specs based on preliminary measurements, and we will further improve things in the future once full data collection and analysis is complete. Dare I point out that the copious amount of press release/collateral/FUD you guys have disseminated over the past year on power is based on "totally meaningless and utterly misleading" (your words) 25C typical data for Virtex-4? You have no worst-case data and you do not have any real power tools for your Virtex-4 customers. I think you should be the one worried about backfire.>The emotional words about benchmarks were no play-acting. I =ADstillhave>scars from Altera's reckless destruction of the old PREPcoo=ADperation,>more than a dozen years ago. And they are still up to their =ADsame old>trickery.I know nothing of PREP (before my time). But if you have specific concerns with the benchmarking methods we use, I'd love to hear them. There is no trickery -- Stratix II has a +39% performance advantage. Regards, Paul Leventis Altera Corp.
