LVDS without termination

Austin Lesea wrote at 2003-10-02 08:03:57 PST
"Also look at what happens when you do not have a 100 ohm termination. 
For some signals, and lengths of pcb, it may not be required." and
"If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few
signals."

I need to get 16 LVDS pairs into one edge of a Spartan-3. This is really 
  simple to layout without termination resistors and really complicated 
(with our board technology) if I add termination resistors.

Without termination the maximum signal length is 4mm. The chip driving 
the LVDS signals uses current mode output drivers.

My question now is what will happen if I try to use LVDS without 
termination? Will the current mode drivers produce a very large output 
signal swing? dangerous overshoot? (They are 3.3V powered)
We want to run data at 480 Mbps over each pair so surely reflections 
with less than 30ps roundtrip time are not that much of a problem?

If the current mode drivers require the 100R at their output, could I 
add them at the source? To get many resistors much closer than 4mm on a 
bga is difficult anyway.

Thank you in advance for your suggestions.

Kolja Sulimma

Kolja Sulimma wrote:
> Austin Lesea wrote at 2003-10-02 08:03:57 PST
> "Also look at what happens when you do not have a 100 ohm
termination.
> For some signals, and lengths of pcb, it may not be required." and
> "If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few
> signals."
>
> I need to get 16 LVDS pairs into one edge of a Spartan-3. This is
really
>   simple to layout without termination resistors and really
complicated
> (with our board technology) if I add termination resistors.
>
> Without termination the maximum signal length is 4mm. The chip
driving
> the LVDS signals uses current mode output drivers.
>
> My question now is what will happen if I try to use LVDS without
> termination? Will the current mode drivers produce a very large
output
> signal swing? dangerous overshoot? (They are 3.3V powered)
> We want to run data at 480 Mbps over each pair so surely reflections
> with less than 30ps roundtrip time are not that much of a problem?
>
This may depend on the drivers, but what I've seen from standard quad
driver chips is that the outputs will eventually drive near the rails,
in your case 3.3V or ground.  Realize that initially the driver is
limited by its impedance and the characteristic impedance of the driven
lines even though they are not terminated.  For longer lines the
voltage
at the driver will rise in small steps separated by the round-trip
delay
time.  For short lines you'll see more of a ramp.
I wouldn't expect much overshoot due to the current limit of the
drivers,
however I would expect problems running at 480 Mbps NRZ.  You may not
have a problem with clock lines, but if data is in one state for
several
bit periods, the voltage that develops may prevent the next signal
transition from happening fast enough.
> If the current mode drivers require the 100R at their output, could I

> add them at the source? To get many resistors much closer than 4mm on
a
> bga is difficult anyway.
For short lines I would say this is a reasonable approach and will work
much better than no termination.
> 
> Thank you in advance for your suggestions.
> 
> Kolja Sulimma

"Gabor" <gabor@alacron.com> schrieb im Newsbeitrag
news:1106924922.935665.312220@f14g2000cwb.googlegroups.com...
> Kolja Sulimma wrote:

> > I need to get 16 LVDS pairs into one edge of a Spartan-3. This is
> really
> >   simple to layout without termination resistors and really
> complicated
> > (with our board technology) if I add termination resistors.

1st) AFAIK LVDS without termination does not work, since the outputs are
CURRENT mode, without a termination no clean output voltage.
2nd) you have Saprtan-3 which has DCI, Digital Controlled Impedance, so no
need for external termination, this can be done inside the FPGA.

Regards
Falk

Kolja,
Oh dear, what claptrap you've had so far in response to your query. IMHO of
course! I guess you get what you pay for! Anyway, here's my guff.
The data rate is somewhat unimportant. What's the rise time of the signals
into your spartan3? Can you tell us what the driving part is?
Also, you should be aware that the trace length on the PCB is only part of
the signal path. There's also the leadframe/BGA package to consider. A rule
of thumb from that Howard Johnson chap, if the total signal path is less
than a sixth of the rise time, you're OK! Electric goes at about 160ps/inch.
Cheers, Syms.
BTW, LVDS/PECL/CML etc. can work without a termination resistor, and the DCI
thing has 'issues'. Browse the Xilinx answers thingy.

Falk Brunner wrote:

> 2nd) you have Saprtan-3 which has DCI, Digital Controlled Impedance, so no
> need for external termination, this can be done inside the FPGA.
 From what I read on this newsgroup LVDS_25_DCI essentially does not 
work if you have many inputs. At least it is not worth the hassle. 
(Webpower estimates 740mA supply current for 16 LVDS_25_SCI inputs at 
480 Mbps).

All the other DCI modes seem to be OK.

Kolja Sulimma

Symon wrote:

> The data rate is somewhat unimportant.
Well, it gives you an upper bound on the rise time.

  What's the rise time of the signals
> into your spartan3? 
They are programmable from 150ps to 400ps.

>Can you tell us what the driving part is?
ADS5270

> Also, you should be aware that the trace length on the PCB is only part of
> the signal path. There's also the leadframe/BGA package to consider. A rule
> of thumb from that Howard Johnson chap, if the total signal path is less
> than a sixth of the rise time, you're OK! Electric goes at about 160ps/inch.
> Cheers, Syms.
Thanks. I am pretty sure that I can disregard transmission line effects 
at these very short signal lengths. What I am concerned about is the 
current mode driver characteristic as described by Gabor.

Kolja

Kolja Sulimma wrote:
> Symon wrote:
>
> > The data rate is somewhat unimportant.
> Well, it gives you an upper bound on the rise time.
>
>   What's the rise time of the signals
> > into your spartan3?
> They are programmable from 150ps to 400ps.
>
> >Can you tell us what the driving part is?
> ADS5270
>
> > Also, you should be aware that the trace length on the PCB is only
part of
> > the signal path. There's also the leadframe/BGA package to
consider. A rule
> > of thumb from that Howard Johnson chap, if the total signal path is
less
> > than a sixth of the rise time, you're OK! Electric goes at about
160ps/inch.
> > Cheers, Syms.
> Thanks. I am pretty sure that I can disregard transmission line
effects
> at these very short signal lengths. What I am concerned about is the
> current mode driver characteristic as described by Gabor.
The parts I was referring to are DS90C031 quad drivers, which are
sort of jelly-bean parts in a package pin-compatible with the venerable
AM26LS31.  These are much slower than the ADS5270 but do have current
source outputs and will drive near the rails with no terminating
resistor.
What bothers me about leaving out terminators, especially in your case
where you're not running 8b/10b or some other code with guaranteed
AC content, is what happens when the output has been in one state long
enough to generate a wide voltage spread.  By the way, LVDS drivers in
FPGA's are not current mode and wouldn't have this problem.  It may
be worth experimenting with the ADS5270 if you have a chance to hook
one
up without a load (maybe on an evaluation module) to see what the
outputs
do without termination.  It would also be interesting to see how the
TI evaluation module handles termination.  The appnotes for the
reference
design from the Xilinx site don't mention the PC board issues.
> 
> Kolja

Kolja Sulimma wrote:
>
>  From what I read on this newsgroup LVDS_25_DCI essentially does not
> work if you have many inputs. At least it is not worth the hassle.
>
If you can live with the power hit and other quirks, it works.

On S3, with the new DCIUpdateMode=Quiet setting, the bank-bank offset
problem should go away. ( although with differential inputs, that
only offsets the common mode of the differential input buffer,
which might(?) have minimal effects on the prop. delay )

Watch the FPGA Cin reflections if you need to get that forwarded clock
to both a local clock input and a global clock input- offhand, I'd do
a flyby of the local clock pins (delay matched to the data lines) with
isolation resistors feeding the local clock input, on to the global
clock pins with provision for a differential attenuator ahead of the
global inputs to damp out the reflection there.

>
> (Webpower estimates 740mA supply current for 16 LVDS_25_SCI
> inputs at 480 Mbps).
>
Watch those mA and mW :)

When I checked just now, Webpower still gives a hopelessly low
static VCCO power estimate of 74 mW per bank overhead and 31 mW per
input pair for S3.

For V2, I found 200 mW per bank and 100 mW per pair far more realistic
estimates of static LVDS_25_DCI power overhead (50 ohm VRP/VRN).

>
> All the other DCI modes seem to be OK.
>
No, all the parallel split termination modes have high power by their
nature.

On a short run, you could try increasing the value of VRP/VRN to maybe
75-100 ohms and see how things look in simulation.

Another possibility to eliminate the per-bank overhead would be to try
disconnecting the VRP/VRN resistors with a timed analog switch after
configuration once the DCI updates have stopped.


Brian

I wrote:
>
> When I checked just now, Webpower still gives a hopelessly low
> static VCCO power estimate of 74 mW per bank overhead and 31 mW per
> input pair for S3.
>
Oops, that should have read "31 mw per input pin" not "per input pair";
i.e., they still seem to be using the 62.5 mW per pair DCI overhead
number in the WebPower estimator tools.

Brian

Hi Gabor,
I think the point is, that with tiny loads on the output, i.e. small traces,
the outputs swing very quickly to whatever voltage the current sources can
provide. This probably remains within the range of the FPGA's diff inputs,
they're very good and wide. I don't see how having 'guaranteed AC content'
makes any difference. Could you explain what you mean by that? Do you mean
enough edges, or no DC?
As you say, I'd certainly have to try it first, the datasheet is not clear
on the output structure. See appnote HFAN-01.0 from Maxim for an overview of
their output structure. Dunno what the Texas one looks like.
On the other hand, I'd be very nervous about doing this. Especially with an
enormous 80 pin PQFP package driving the outputs. Again, think of the
hideous leadframe. Like you say, you'd have to prototype it first.
Kolja,
You do know that you can get 8x100 resistors in two packs sized 2x1mm? Rohm,
AVX, Koa etc.. have gone to a lot of trouble to make these bits. Use them!
http://www.avx.com/docs/Catalogs/crb-crc.pdf
And fix your PCB technology, your competitors will!
Cheers, Syms.

"Gabor" <gabor@alacron.com> wrote in message
news:1107179024.417762.98680@f14g2000cwb.googlegroups.com...
>
> > at these very short signal lengths. What I am concerned about is the
> > current mode driver characteristic as described by Gabor.
> What bothers me about leaving out terminators, especially in your case
> where you're not running 8b/10b or some other code with guaranteed
> AC content, is what happens when the output has been in one state long
> enough to generate a wide voltage spread.