Help on a FPGA design

Verilog Instantiation Template

// BSCAN_SPARTAN3:Boundary Scan primitve for connecting internal logic // JTAG interface. Spartan-II // Xilinx HDL Libraries Guide version 7.1i

BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst ( .CAPTURE(CAPTURE), .DRCK1(DRCK1), .DRCK2(DRCK2), .RESET(RESET), .SEL1(SEL1), .SEL2(SEL2), .SHIFT(SHIFT), .TDI(TDI), .UPDATE(UPDATE), .TDO1(TDO1), .TDO2(TDO2) );

Ann wrote:
> Hm...I read something about the USER1 and USER2 registers and also
found this code in the software manual Verilog Instantiation Template
>
> // BSCAN_SPARTAN3:Boundary Scan primitve for connecting internal
logic // JTAG interface. Spartan-II // Xilinx HDL Libraries Guide
version 7.1i BSCAN_SPARTAN3 BSCAN_SPARTAN3_inst ( .CAPTURE(CAPTURE), //
CAPTURE output from TAP //controller .DRCK1(DRCK1), // Data register
output - //USER1 functions .DRCK2(DRCK2), // Data register output -
//USER2 functions .RESET(RESET), // Reset output from //TAP controller
.SEL1(SEL1), // USER1 active output .SEL2(SEL2), // USER2 active output
.SHIFT(SHIFT), // SHIFT output from //TAP controller .TDI(TDI), // TDI
output from // TAP controller .UPDATE(UPDATE), // UPDATE output from
//TAP controller .TDO1(TDO1), // Data input for USER1 //function
.TDO2(TDO2) // Data input for USER2 //function ); Has anyone used this
feature before? Does it work in reading out a user defined register? If
you know anything about this feature, please let me know.
>
> Thanks, Ann

I used to use this in the original spartan parts (XC4000-like).  But I
thought
it had disappeared from newer parts.  If they still have a BSCAN
primitive you should find it easier than reading out the whole config.
However be aware that at least in the old parts, placing the BSCAN into
the design made it hard to re-program the part if you needed to use
JTAG for that, too (I was using
slave serial mode).

Hi Gabor,

Did you remember how to do it? Do you have example code? I don't understand the inputs and outputs in the example that I posted above. Is it true that all I need is to put an instance of BSCAN in the code?

Hi Ann,

I'm not sure what you are trying to do, but maybe the techXclusives article 
on reconfiguring block RAMs below will help.

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=krs_blockRAM

Philip Nowe
www.dulseelectronics.com

"Ann" <ann.lai@analog.com> wrote in message news:ee8b8e5.11@webx.sUN8CHnE...
> Hi Gabor,
>
> Did you remember how to do it? Do you have example code? I don't 
> understand the inputs and outputs in the example that I posted above. Is 
> it true that all I need is to put an instance of BSCAN in the code? 

Hi, thanks for all the help. The application on Reconfiguring block of RAMs was very helpful, and also app139. I thought I already have it figured out, but I am running into a weird problem with this bscan_spartan3 module. When I put a constant number into the register and read it back, it works, but when I have that number changed depending on the rising edge of the clock, and a RESET signal or something, it doesn't work anymore. For example, in the following code: always @(posedge CLK_IN) begin					 	if(RESET) 	begin 		num = 20+1; 	end 	else				 	begin 		num = 1+1; 	end It would give me 00010011 or 21 even though the RESET signal has changed. I tried using the CASE statement instead: always @(posedge CLK_IN) begin	 case(RESET) 	2'd0: num = 20+1; 	2'd1: num = 2+2; 	default: num = 3+4; 	endcase end Now it always gives me 00000000 when I tried to read it back. Do you have any idea why? Thanks, Ann