USB 1.1/2.0 Implementation

Hi All

Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in Altera
Device. If yes, can you pls start me off. I'm not able to make any progress
in this. I have found couple of sites in ths area, but always end towards a
brick wall.

Help Pls

Cheerio

"SneakerNet" <nospam@nospam.org> wrote in message news:<fIObb.156268$JA5.3828849@news.xtra.co.nz>...
> Hi All
> 
> Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in Altera
> Device. If yes, can you pls start me off. I'm not able to make any progress
> in this. I have found couple of sites in ths area, but always end towards a
> brick wall.

if you dont say what your problem is how could one help?
the USB cores available are working out of box for Xilinx, for altera
you need to change the technology dependant portions and it should
again work.

antti

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309222237.7c93ed9a@posting.google.com...
> "SneakerNet" <nospam@nospam.org> wrote in message
news:<fIObb.156268$JA5.3828849@news.xtra.co.nz>...
> > Hi All
> >
> > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
Altera
> > Device. If yes, can you pls start me off. I'm not able to make any
progress
> > in this. I have found couple of sites in ths area, but always end
towards a
> > brick wall.
>
> if you dont say what your problem is how could one help?
> the USB cores available are working out of box for Xilinx, for altera
> you need to change the technology dependant portions and it should
> again work.
>
> antti

Hi Antti
Thanks for the response. I actually contacted you regarding USB page that
you mentioned in this newsgroup a while back (Japanese language).
Ok firstly regarding USB implementation, the way I see it, there are 3 major
parts, which are:
1. USB Transceiver (to connect the FPGA and the PC)
2. FPGA Implementation
3. Windows App

Now
1. USB Transceiver - I have found out that the Philips PDIUSBP11A is quite
suitable for this job. However if you look at this pdf (which shows the
circuit connection) www.semiconductors.philips.com/acrobat/
applicationnotes/AN10007-01.pdf  , on page 5 of this pdf there are 2 circuit
diagrams. I'm not able to understand the difference between upstream and
downstream circuits. Pls help/advice.
2. FPGA Implementation - Antti, you replyed saying (for altera you need to
change the technology dependant portions and it should again work.). What do
you mean by this? Help Again. Where can I download the USB cores to begin
with? Once I can get hold of the USB core, I guess I'll have a starting
point.
3. Windows Implementation - I have no clue with regards to windows drivers.
Any help in this matter would be very greatful.

Thanks guys

SneakerNet wrote:
> 
> "Antti Lukats" <antti@case2000.com> wrote in message
> news:80a3aea5.0309222237.7c93ed9a@posting.google.com...
> > "SneakerNet" <nospam@nospam.org> wrote in message
> news:<fIObb.156268$JA5.3828849@news.xtra.co.nz>...
> > > Hi All
> > >
> > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> Altera
> > > Device. If yes, can you pls start me off. I'm not able to make any
> progress
> > > in this. I have found couple of sites in ths area, but always end
> towards a
> > > brick wall.
> >
> > if you dont say what your problem is how could one help?
> > the USB cores available are working out of box for Xilinx, for altera
> > you need to change the technology dependant portions and it should
> > again work.
> >
> > antti
> 
> Hi Antti
> Thanks for the response. I actually contacted you regarding USB page that
> you mentioned in this newsgroup a while back (Japanese language).
> Ok firstly regarding USB implementation, the way I see it, there are 3 major
> parts, which are:
> 1. USB Transceiver (to connect the FPGA and the PC)
> 2. FPGA Implementation
> 3. Windows App
> 
> Now
> 1. USB Transceiver - I have found out that the Philips PDIUSBP11A is quite
> suitable for this job. However if you look at this pdf (which shows the
> circuit connection) www.semiconductors.philips.com/acrobat/
> applicationnotes/AN10007-01.pdf  , on page 5 of this pdf there are 2 circuit
> diagrams. I'm not able to understand the difference between upstream and
> downstream circuits. Pls help/advice.

I have not looked at the circuits, but upstream is closer to the PC and
so is a "host" type connection while downstream is closer to (or is) the
peripheral.  I think there are only very small differences having to do
with initialization protocol.  


> 2. FPGA Implementation - Antti, you replyed saying (for altera you need to
> change the technology dependant portions and it should again work.). What do
> you mean by this? Help Again. Where can I download the USB cores to begin
> with? Once I can get hold of the USB core, I guess I'll have a starting
> point.

I think he was saying that he is aware of IP that works in the Xilinx
chips and so would work in any other FPGA.  But the coding style may
have used chip specific features (like the 16 bit SRL in the Xilinx
parts).  If so, this code may need to be changed to something more
generic for an Altera part.  Any Xilinx features that are instantiated
will need to be replaced for sure.  

Check www.opencores.org.  They have USB 1.1 and 2.0 implementations
available.  I don't know if they are vendor specific or not.  


> 3. Windows Implementation - I have no clue with regards to windows drivers.
> Any help in this matter would be very greatful.

This depends on your application.  I believe there is a generic set of
drivers to support a "human interface device" or similar which means it
works like a mouse or keyboard in terms of sending data in small
packets.  

Again, I am not directly experienced with this, but I have been
listening intently when others discuss this here and elsewhere.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3F710E81.AB8E310F@yahoo.com...
> SneakerNet wrote:
> >
> > "Antti Lukats" <antti@case2000.com> wrote in message
> > news:80a3aea5.0309222237.7c93ed9a@posting.google.com...
> > > "SneakerNet" <nospam@nospam.org> wrote in message
> > news:<fIObb.156268$JA5.3828849@news.xtra.co.nz>...
> > > > Hi All
> > > >
> > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> > Altera
> > > > Device. If yes, can you pls start me off. I'm not able to make any
> > progress
> > > > in this. I have found couple of sites in ths area, but always end
> > towards a
> > > > brick wall.
> > >
> > > if you dont say what your problem is how could one help?
> > > the USB cores available are working out of box for Xilinx, for altera
> > > you need to change the technology dependant portions and it should
> > > again work.
> > >
> > > antti
> >
> > Hi Antti
> > Thanks for the response. I actually contacted you regarding USB page
that
> > you mentioned in this newsgroup a while back (Japanese language).
> > Ok firstly regarding USB implementation, the way I see it, there are 3
major
> > parts, which are:
> > 1. USB Transceiver (to connect the FPGA and the PC)
> > 2. FPGA Implementation
> > 3. Windows App
> >
> > Now
> > 1. USB Transceiver - I have found out that the Philips PDIUSBP11A is
quite
> > suitable for this job. However if you look at this pdf (which shows the
> > circuit connection) www.semiconductors.philips.com/acrobat/
> > applicationnotes/AN10007-01.pdf  , on page 5 of this pdf there are 2
circuit
> > diagrams. I'm not able to understand the difference between upstream and
> > downstream circuits. Pls help/advice.
>
> I have not looked at the circuits, but upstream is closer to the PC and
> so is a "host" type connection while downstream is closer to (or is) the
> peripheral.  I think there are only very small differences having to do
> with initialization protocol.

Thanks for the clarification.

>
>
> > 2. FPGA Implementation - Antti, you replyed saying (for altera you need
to
> > change the technology dependant portions and it should again work.).
What do
> > you mean by this? Help Again. Where can I download the USB cores to
begin
> > with? Once I can get hold of the USB core, I guess I'll have a starting
> > point.
>
> I think he was saying that he is aware of IP that works in the Xilinx
> chips and so would work in any other FPGA.  But the coding style may
> have used chip specific features (like the 16 bit SRL in the Xilinx
> parts).  If so, this code may need to be changed to something more
> generic for an Altera part.  Any Xilinx features that are instantiated
> will need to be replaced for sure.
>
> Check www.opencores.org.  They have USB 1.1 and 2.0 implementations
> available.  I don't know if they are vendor specific or not.
>

Err.. I found this usb_phy from opencores.org however I'm struggling with
that. The main top layer file has so many I/O's compared to the I/Os of the
PDIUSBP11A, i'm stuck. I'm stuck in the sense that I do not know which pin
will map which one on the transcevier.

>
> > 3. Windows Implementation - I have no clue with regards to windows
drivers.
> > Any help in this matter would be very greatful.
>
> This depends on your application.  I believe there is a generic set of
> drivers to support a "human interface device" or similar which means it
> works like a mouse or keyboard in terms of sending data in small
> packets.
>
> Again, I am not directly experienced with this, but I have been
> listening intently when others discuss this here and elsewhere.

Sigh.. I guess I'll join you ..

Thanks for your input.

>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

"SneakerNet" <nospam@nospam.org> wrote in message news:<p43cb.157047
> Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
[deleted]

USB11T11A FS/LS USB tranceiver

usb_phy (opencores) UTMI interface that connects to USB11T11A

usb1.1 (opencores) connects to usb_phy (opencores) connects to
USB11T1A it is not HID but it will enumerate in hardware iw the USB
host will 'see' it, but ther is no host software provide

usb (japanase desing) full HID USB core includes USB11T1A model) can
directly be connected to usb D+ D- pins! (no tranceiver chip), there
is some VB test program to talk to the core (as it is HID peripheral)

antti
PS I am afraid you have todo some homework :) cant do it for you

Hi Antti
Thanks for the response.
haha. I don't expect anyone to do work for me, othwersie I won't learn
anything, but I wouldn't mind some guidance along the way from you guys..
Anyway I need to ask 2 questions regarding your reply.
1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
gone blind?
2. Regarding the usb (japanese design), I have ended up towards a brick
wall. What I mean to say is, I have been looking at the design for couple of
hours and there are 4 components that I'm not sure what they do. The main
problem is that the code was written for a Xilinx component and because I'm
using Altera component, I'm do not have the librabires that these component
are using.
Firstly the library defined is (which is for Xilinx only (pls correct me if
i'm wrong))
library unisim;
use unisim.vcomponents.all;

and the 4 components that are using this library are
u_DLL : CLKDLL
    port map (    CLKIN => CLKINM,
                        CLKFB => GCLK,
                        RST => RST,
                        CLK0 => GCLKM,
                        CLK2X => CLKM,
                        LOCKED => LOCK
                    );

u_GCLK : BUFG
    port map (    I => GCLKM,
                        O => GCLK
                    );

u_CLK : BUFG
    port map (    I => CLKM,
                        O => CLK
                    );

u_CLKIN : IBUFG
    port map (    I => CLKIN,
                        O => CLKINM
                    );

If you can explain me how I can replace these components for Altera design,
I will have a step to progress. If I can get past this point, then I have
something to try on the chip and play around. My problem is that right now I
can't go past compiling as Quartus doesn't recognize these components (or
the library). Pls Advice

Thanks again

Regards


"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309240119.7925b682@posting.google.com...
> "SneakerNet" <nospam@nospam.org> wrote in message news:<p43cb.157047
> > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> [deleted]
>
> USB11T11A FS/LS USB tranceiver
>
> usb_phy (opencores) UTMI interface that connects to USB11T11A
>
> usb1.1 (opencores) connects to usb_phy (opencores) connects to
> USB11T1A it is not HID but it will enumerate in hardware iw the USB
> host will 'see' it, but ther is no host software provide
>
> usb (japanase desing) full HID USB core includes USB11T1A model) can
> directly be connected to usb D+ D- pins! (no tranceiver chip), there
> is some VB test program to talk to the core (as it is HID peripheral)
>
> antti
> PS I am afraid you have todo some homework :) cant do it for you

SneakerNet wrote:
> 
> Hi Antti
> Thanks for the response.
> haha. I don't expect anyone to do work for me, othwersie I won't learn
> anything, but I wouldn't mind some guidance along the way from you guys..
> Anyway I need to ask 2 questions regarding your reply.
> 1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
> no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
> gone blind?
> 2. Regarding the usb (japanese design), I have ended up towards a brick
> wall. What I mean to say is, I have been looking at the design for couple of
> hours and there are 4 components that I'm not sure what they do. The main
> problem is that the code was written for a Xilinx component and because I'm
> using Altera component, I'm do not have the librabires that these component
> are using.
> Firstly the library defined is (which is for Xilinx only (pls correct me if
> i'm wrong))
> library unisim;
> use unisim.vcomponents.all;
> 
> and the 4 components that are using this library are
> u_DLL : CLKDLL
>     port map (    CLKIN => CLKINM,
>                         CLKFB => GCLK,
>                         RST => RST,
>                         CLK0 => GCLKM,
>                         CLK2X => CLKM,
>                         LOCKED => LOCK
>                     );
> 
> u_GCLK : BUFG
>     port map (    I => GCLKM,
>                         O => GCLK
>                     );
> 
> u_CLK : BUFG
>     port map (    I => CLKM,
>                         O => CLK
>                     );
> 
> u_CLKIN : IBUFG
>     port map (    I => CLKIN,
>                         O => CLKINM
>                     );
> 
> If you can explain me how I can replace these components for Altera design,
> I will have a step to progress. If I can get past this point, then I have
> something to try on the chip and play around. My problem is that right now I
> can't go past compiling as Quartus doesn't recognize these components (or
> the library). Pls Advice

This is something I know a bit more about.  These are all clock
components.  CLKDLL is a DLL (Delay Locked Loop) like a PLL only more
Xilinx like ;)  The Altera parts have PLLs depending on the part.  I
don't know if this is required or just used to allow different external
and internal clock rates.  

The BUFG and IBUFG are just clock buffers.  They are used to drive the
internal clock distribution networks.  Altera should have equivalent
components or you may not need to instantiate them since they are
typically locked to a given pin and should be inferred by most tools. 
Read up a bit on the Xilinx and Altera chips and this will all be very
clear.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Hi SneakerNet,

I just noticed we have VERY handy application note for you -- AN307
(available on www.altera.com) describes how to migrate from a Xilinx design
to an Altera design.  There is a section dedicated to DLL to PLL conversion
that should be able to help you out.  Below is my attempt at explaining
things before I found this app note.

In Altera's FPGAs, we've got PLLs, which provide a superset of the CLKDLL
function you're trying to use.  You'd want to setup your PLL to use CLKIN as
its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK
signal, don't apply any phase shift, and use the C0 port to compensate the
PLL output.  Connect RST to the areset port, and LOCKED to the locked port.
You'll want to setup your C1 port to have a 2x frequency multiplier on it.
The Lock and Reset signals have some sort of equivalent that I can't recall.
You can do this all through the allpll megafunction.

The BUFGs are not necessary in Altera parts.  In Xilinx parts, these buffers
are needed to explicitly indicate that you want a signal to be driven onto
the global clock network.  Quartus allows you to make "global" assignments
to nets, but it automatically promotes anything it finds that looks like a
clock net, as well as high-fanout or asynchronous signals if there are
enough global clocks available.  The PLL output nets will be automatically
promoted to global clock nets for you, and the PLL input will be assigned to
the associated input clock pin.

Also, I should point out that there are four USB cores listed on our
Intellectual Property page (www.altera.com) under Interfaces & Peripherals
under USB.  All are available for free trial under our OpenCore evaluation
program.

Regards,

Paul Leventis
Altera Corp.


"SneakerNet" <nospam@nospam.org> wrote in message
news:h9ocb.158045$JA5.3882825@news.xtra.co.nz...
> Hi Antti
> Thanks for the response.
> haha. I don't expect anyone to do work for me, othwersie I won't learn
> anything, but I wouldn't mind some guidance along the way from you guys..
> Anyway I need to ask 2 questions regarding your reply.
> 1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A?
If
> no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
> gone blind?
> 2. Regarding the usb (japanese design), I have ended up towards a brick
> wall. What I mean to say is, I have been looking at the design for couple
of
> hours and there are 4 components that I'm not sure what they do. The main
> problem is that the code was written for a Xilinx component and because
I'm
> using Altera component, I'm do not have the librabires that these
component
> are using.
> Firstly the library defined is (which is for Xilinx only (pls correct me
if
> i'm wrong))
> library unisim;
> use unisim.vcomponents.all;
>
> and the 4 components that are using this library are
> u_DLL : CLKDLL
>     port map (    CLKIN => CLKINM,
>                         CLKFB => GCLK,
>                         RST => RST,
>                         CLK0 => GCLKM,
>                         CLK2X => CLKM,
>                         LOCKED => LOCK
>                     );
>
> u_GCLK : BUFG
>     port map (    I => GCLKM,
>                         O => GCLK
>                     );
>
> u_CLK : BUFG
>     port map (    I => CLKM,
>                         O => CLK
>                     );
>
> u_CLKIN : IBUFG
>     port map (    I => CLKIN,
>                         O => CLKINM
>                     );
>
> If you can explain me how I can replace these components for Altera
design,
> I will have a step to progress. If I can get past this point, then I have
> something to try on the chip and play around. My problem is that right now
I
> can't go past compiling as Quartus doesn't recognize these components (or
> the library). Pls Advice
>
> Thanks again
>
> Regards
>
>
> "Antti Lukats" <antti@case2000.com> wrote in message
> news:80a3aea5.0309240119.7925b682@posting.google.com...
> > "SneakerNet" <nospam@nospam.org> wrote in message news:<p43cb.157047
> > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> > [deleted]
> >
> > USB11T11A FS/LS USB tranceiver
> >
> > usb_phy (opencores) UTMI interface that connects to USB11T11A
> >
> > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > USB11T1A it is not HID but it will enumerate in hardware iw the USB
> > host will 'see' it, but ther is no host software provide
> >
> > usb (japanase desing) full HID USB core includes USB11T1A model) can
> > directly be connected to usb D+ D- pins! (no tranceiver chip), there
> > is some VB test program to talk to the core (as it is HID peripheral)
> >
> > antti
> > PS I am afraid you have todo some homework :) cant do it for you
>
>

Hello again Paul ;o)

LOL, tell you what, I already cracked it. I found that document sometime
back now *grins*.
And I also cracked that the CLKDLL is just a pll *grins again* and thus I
had posted another msg (which you have already replied before) but once
again I beat you to it. I cracked it before you replied ;o).

Anyway thanks for taking time in explaning the Xilinx components.
Regarding the free USB Cores from Altera website.
Service I would give umm 10% *no offence*. I had to log into that page and
request the core nearly 10 times before someone contacted me from Altera.
Then after 2-3 days they told me that USB 2.0 core is not functional so i
asked for usb 1.1 core. Then they asked me hundreds of questions of why/what
for/how long etc etc. When I finally got it, it was only licenced for a
month (which passes by just like that as I'm working on this USB project
part time.
Anyway I found a site that had the full VHDL USB core free of cost (without
any need for any hardware). I'm stuck at the windows driver now. Rest is all
ready to go..

Any help on how to install a generic usb driver?

Thanks for your response Paul.
Bye

"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message
news:IK6eb.162179$Lnr1.32740@news01.bloor.is.net.cable.rogers.com...
> Hi SneakerNet,
>
> I just noticed we have VERY handy application note for you -- AN307
> (available on www.altera.com) describes how to migrate from a Xilinx
design
> to an Altera design.  There is a section dedicated to DLL to PLL
conversion
> that should be able to help you out.  Below is my attempt at explaining
> things before I found this app note.
>
> In Altera's FPGAs, we've got PLLs, which provide a superset of the CLKDLL
> function you're trying to use.  You'd want to setup your PLL to use CLKIN
as
> its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK
> signal, don't apply any phase shift, and use the C0 port to compensate the
> PLL output.  Connect RST to the areset port, and LOCKED to the locked
port.
> You'll want to setup your C1 port to have a 2x frequency multiplier on it.
> The Lock and Reset signals have some sort of equivalent that I can't
recall.
> You can do this all through the allpll megafunction.
>
> The BUFGs are not necessary in Altera parts.  In Xilinx parts, these
buffers
> are needed to explicitly indicate that you want a signal to be driven onto
> the global clock network.  Quartus allows you to make "global" assignments
> to nets, but it automatically promotes anything it finds that looks like a
> clock net, as well as high-fanout or asynchronous signals if there are
> enough global clocks available.  The PLL output nets will be automatically
> promoted to global clock nets for you, and the PLL input will be assigned
to
> the associated input clock pin.
>
> Also, I should point out that there are four USB cores listed on our
> Intellectual Property page (www.altera.com) under Interfaces & Peripherals
> under USB.  All are available for free trial under our OpenCore evaluation
> program.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
>
> "SneakerNet" <nospam@nospam.org> wrote in message
> news:h9ocb.158045$JA5.3882825@news.xtra.co.nz...
> > Hi Antti
> > Thanks for the response.
> > haha. I don't expect anyone to do work for me, othwersie I won't learn
> > anything, but I wouldn't mind some guidance along the way from you
guys..
> > Anyway I need to ask 2 questions regarding your reply.
> > 1. When you say USB11T11A, do you mean the Philips tranceiver
PDIUSBP11A?
> If
> > no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
> > gone blind?
> > 2. Regarding the usb (japanese design), I have ended up towards a brick
> > wall. What I mean to say is, I have been looking at the design for
couple
> of
> > hours and there are 4 components that I'm not sure what they do. The
main
> > problem is that the code was written for a Xilinx component and because
> I'm
> > using Altera component, I'm do not have the librabires that these
> component
> > are using.
> > Firstly the library defined is (which is for Xilinx only (pls correct me
> if
> > i'm wrong))
> > library unisim;
> > use unisim.vcomponents.all;
> >
> > and the 4 components that are using this library are
> > u_DLL : CLKDLL
> >     port map (    CLKIN => CLKINM,
> >                         CLKFB => GCLK,
> >                         RST => RST,
> >                         CLK0 => GCLKM,
> >                         CLK2X => CLKM,
> >                         LOCKED => LOCK
> >                     );
> >
> > u_GCLK : BUFG
> >     port map (    I => GCLKM,
> >                         O => GCLK
> >                     );
> >
> > u_CLK : BUFG
> >     port map (    I => CLKM,
> >                         O => CLK
> >                     );
> >
> > u_CLKIN : IBUFG
> >     port map (    I => CLKIN,
> >                         O => CLKINM
> >                     );
> >
> > If you can explain me how I can replace these components for Altera
> design,
> > I will have a step to progress. If I can get past this point, then I
have
> > something to try on the chip and play around. My problem is that right
now
> I
> > can't go past compiling as Quartus doesn't recognize these components
(or
> > the library). Pls Advice
> >
> > Thanks again
> >
> > Regards
> >
> >
> > "Antti Lukats" <antti@case2000.com> wrote in message
> > news:80a3aea5.0309240119.7925b682@posting.google.com...
> > > "SneakerNet" <nospam@nospam.org> wrote in message news:<p43cb.157047
> > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> > > [deleted]
> > >
> > > USB11T11A FS/LS USB tranceiver
> > >
> > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > >
> > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > USB11T1A it is not HID but it will enumerate in hardware iw the USB
> > > host will 'see' it, but ther is no host software provide
> > >
> > > usb (japanase desing) full HID USB core includes USB11T1A model) can
> > > directly be connected to usb D+ D- pins! (no tranceiver chip), there
> > > is some VB test program to talk to the core (as it is HID peripheral)
> > >
> > > antti
> > > PS I am afraid you have todo some homework :) cant do it for you
> >
> >
>
>