See the next high-wire act, this time on power consumption

Thank you if you watched the previous story on Virtex-4 performance.
Now please click on
http://seminar2.techonline.com/s/xilinx_feb1505
and sign up for the next presentation in this series, where Matt Klein
of Xilinx Applications will explain the three aspects of power
consumption. This is again an engineering presentation: Matt has been a
"power user" of Xilinx FPGAs for over 17 years, he even published a
Xilinx app note in 1990, while working at hp. We have been friends
since 1988, and I was thrilled when he decided to join Xilinx
Applications last year.

The previous talk on performance had excellent participation, and a
spirited follow-up debate in this newsgroup. Thank you, Paul, for
providing spice with the contrary point of view !
I hope many of you will join us again coming Tuesday at noon, Pacific
Time.

Peter Alfke, Xilinx Applications

We have finished our PPT slides and polished the presentation. It will
be tutorial and technical in nature, but will also not shy away from
competitive issues. I will play host, and Matt Klein will give the
presentation. No accent, and hopefully no audio problems...
My previous posting indicated the wrong time,
it's really at 11:00 am Pacific Time this coming Tuesday, Feb 15.
Hope you can join us for this and the subsequent seminars in this
series.

Peter Alfke, Xilinx Applications

> We have finished our PPT slides and polished the presentation. It
will
> be tutorial and technical in nature, but will also not shy away from
> competitive issues.

Too bad the slides are done given that we've released updated power
specs.  I'm sure you will carefully caveat the comparison
appropriately...

BTW, I sincerely hope you will stop all this nonsense with in-rush
"power".  Your web site seems to trumpet a big advantage here, but
Stratix II does not have any in-rush current (as announced a few weeks
back).  Never mind that in-rush "power" is meaningless -- in chips that
do have an in-rush event, it is just a temporary spike in *current*
draw during power up and in no way relates to thermal dissipation or
energy requirements of the device.  All this spike affects is the
minimum supply size from a transient current perspective.

I personally think it was slimy to take what was a conservative minimum
power supply size spec and convert it into Watts and pretend it was a
power consumption.  But I guess that's marketing...  Anyway, it is moot
given there is no inrush in Stratix II.

Good luck tomorrow.  I'm looking forward to a very healthy debate
afterwards :-)

Paul Leventis
Altera Corp.

Paul,

In denial, huh?

No surge, just an insignificant little spike?

No power.

Yes, but do you need it to turn on?  If you do, the power vendors just 
love you, as they get to sell bigger power supplies.  You got a surge.

If the spike is an artifact, and it is only current that is consumed if 
available, and if and only if all the current that is required is the 
leakage to turn the device on, then you have no surge.

So, I am willing to grant you fixed it, as it can be fixed (like we did 
back with V2) as it is fixable.

But prove it.  Where is the scope shot?

But, you did not use a third oxide transistor, and the result is the 
huge static leakage with increasing temperature.

Enjoy,

Austin



Paul Leventis wrote:

>>We have finished our PPT slides and polished the presentation. It
> 
> will
> 
>>be tutorial and technical in nature, but will also not shy away from
>>competitive issues.
> 
> 
> Too bad the slides are done given that we've released updated power
> specs.  I'm sure you will carefully caveat the comparison
> appropriately...
> 
> BTW, I sincerely hope you will stop all this nonsense with in-rush
> "power".  Your web site seems to trumpet a big advantage here, but
> Stratix II does not have any in-rush current (as announced a few weeks
> back).  Never mind that in-rush "power" is meaningless -- in chips that
> do have an in-rush event, it is just a temporary spike in *current*
> draw during power up and in no way relates to thermal dissipation or
> energy requirements of the device.  All this spike affects is the
> minimum supply size from a transient current perspective.
> 
> I personally think it was slimy to take what was a conservative minimum
> power supply size spec and convert it into Watts and pretend it was a
> power consumption.  But I guess that's marketing...  Anyway, it is moot
> given there is no inrush in Stratix II.
> 
> Good luck tomorrow.  I'm looking forward to a very healthy debate
> afterwards :-)
> 
> Paul Leventis
> Altera Corp.
> 

Hi you Rottweilers, back into your cages!
 We have not even started our presentation. and Paul is already playing
umpire. We based our evaluations not only on those published numbers
that Altera can change at will, if they are prepared to back them up,
and to guarantee them. It is, however, just a little strange that their
leakage current evaporated the very moment Xilinx announced a seminar
about it. Cause and effect ? Marketing jitters?

We also did made extensive real physical measurements, which we will
report. And they cannot be prettied up by a press release.

But why don't you all relax and listen what we have to say. There is
plenty of space in this newsgroup for a rebuttal, and a re-rebuttal and
a re-re-rebuttal. But remember, hot air just makes the current go up.
If all this really produces low-static-power 90 nm devices, users
should be happy.
Peter Alfke, Xilinx

Paul Leventis wrote:

>>We have finished our PPT slides and polished the presentation. It
> will be tutorial and technical in nature, but will also not shy away from
>>competitive issues.
> 
> 
> Too bad the slides are done given that we've released updated power
> specs.  I'm sure you will carefully caveat the comparison
> appropriately...

If you mean these numbers, from 31 Jan, :
http://www.altera.com/corporate/news_room/releases/products/nr-perf_power.html

then I am sure Peter, et al, will have included those, in their PPT 
slides. This is a Feb 2005 comparison, after all ?

If you mean this one, from 14 Feb
http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html

that's a harder call. Are these actually the SAME numbers, (press 
released twice) or has two weeks resulted in another improvement ?.

They don't quite overlay, as the Jan spec says 45%, but the Feb one is 
47%, or is that 'really the same number' to marketing ?

-jg

> If you mean this one, from 14 Feb
>
http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html
>
> that's a harder call. Are these actually the SAME numbers, (press
> released twice) or has two weeks resulted in another improvement ?.

I don't expect Xilinx to include these numbers.  They were after all
just released yesterday.

> They don't quite overlay, as the Jan spec says 45%, but the Feb one
is
> 47%, or is that 'really the same number' to marketing ?

Two seperate releases for two seperate improvements.  EPE 2.0 had a up
to 45% reduction vs. 1.0, and EPE 2.1 has a up to 47% reduction vs. EPE
2.0.  Sorry for the up to numbers -- the results do vary a lot across
process, temperature and device used.

Paul Leventis
Altera Corp.

Austin,

I am an engineer.  I do not knowingly put my name on a spec that could
lead to system failures.  When I say we do not have a power up surge,
and that users only need to size their power supply to meet the
operating requirements of the chip, I mean it.  This is based on the
data we have measured over a variety of conditions and ordering for
power supply ramp up.

> In denial, huh?

Are you this annoying in real life?

You thought you had a big advantage on this in-rush business (which was
overblown anyway).  You do not have an advantage here.  Get over it and
find something else to harp on.

Paul Leventis
Altera Corp.

Hi Peter,

Ah!  I'm being tag teamed!  :-)

> If they are prepared to back them up,
> and to guarantee them.

We guarentee all our specs.  That is why we start with conservative
estimates, and tighten the specs over time.  You see this with our
static power data.  And you see this with our maximum Fmax specs.  It
is how we do things.  This sucks for marketing, but it means our
customer designs work.

I can't expect you to stop liberally interpreting our specs.  But I
think we should all draw the line at questioning whether either company
is cooking the numbers.

> It is, however, just a little strange that their
> leakage current evaporated the very moment Xilinx announced a seminar
> about it. Cause and effect ? Marketing jitters?

I have no control over when we release data.  But I can assure you that
the data collection and analysis was going on long before your seminar
announcement -- it is part of our on-going characterization.  Now that
we have all family members out, we have the data we need to update our
specs.

Paul Leventis
Altera Corp.

Paul,

OK.  I'll reserve my judgement until I see the scope pictures.

No more comments on power ON surge.

And, yes, I have been told that I am extremely annoying 'in real life.'

Usually by people that are trying to divert attention from real issues.

Austin

Paul Leventis wrote:
> Austin,
> 
> I am an engineer.  I do not knowingly put my name on a spec that could
> lead to system failures.  When I say we do not have a power up surge,
> and that users only need to size their power supply to meet the
> operating requirements of the chip, I mean it.  This is based on the
> data we have measured over a variety of conditions and ordering for
> power supply ramp up.
> 
> 
>>In denial, huh?
> 
> 
> Are you this annoying in real life?
> 
> You thought you had a big advantage on this in-rush business (which was
> overblown anyway).  You do not have an advantage here.  Get over it and
> find something else to harp on.
> 
> Paul Leventis
> Altera Corp.
>