2 microblaze access same BRAM ?

hello

I want to map two microblaes into FPGA. Problem is that I do not aware
that it is possible to use one LMB and one dual port BRAM for two
microblazes so that two microblazes share memory address space. Does
anyone have this experience ?

Hi,

There should be no problem with this.
Just add two bram blocks and connected MicroBlaze1 and MicroBlaze2 instruction 
LMB buses to the first bram's two ports.
Then do the same for the data LMB buses for the second bram block.

This can all be done in Xilinx Platform Studio (XPS).

G�ran Bilski

Elinore wrote:
> hello
> 
> I want to map two microblaes into FPGA. Problem is that I do not aware
> that it is possible to use one LMB and one dual port BRAM for two
> microblazes so that two microblazes share memory address space. Does
> anyone have this experience ?
> 

hi

It is good be feasible. I found that in XPS wizard we can set maximaly
64 KB for BRAM. Subsequent question is about the size. Can we make it
bigger, for example 128KB or 256 KB ? 

Thankyou again

Yes, Just have multiple bram blocks and bram controllers.

G�ran

Elinore wrote:
> hi
> 
> It is good be feasible. I found that in XPS wizard we can set maximaly
> 64 KB for BRAM. Subsequent question is about the size. Can we make it
> bigger, for example 128KB or 256 KB ? 
> 
> Thankyou again
> 

i like this 'great' flexibility in FPGA. In this context, i dare to
make more 'what if' questions (to me, to others)....

What if we have 2 microblazes (uBLAZE0, uBLAZE1) with  BRAM0 and BRAM1,
respectively. Suppose BRAM0 ranges 0x00000000 - 0x00003ffff and BRAM1
ranges 0x00004000 - 0x00007ffff. The uBLAZE0 wanna access BRAM1 using
shared variable so that programmar see 2 BRAMs as one big global
memory. Then problem will be bus  ( memory access ) arbitration. So we
may need a special hardware. Writing an application code will be uneasy
as well, because we will need only one main routine. How can we utilize
xilinx-provided design resources to do those? This seems to be very
hard but interesting ......

Hi,

Let see if I got this right.
You have two MicroBlazes and the bram blocks.
I assume that the bram blocks are shared as the original question ask about.

If the uses one port each from each BRAM there is no arbitration since each bus 
only have one master (one of the MicroBlazes).

They will share the whole memory range 0x00000000 - 0x00007fff.

So this is easily handled in the XPS.

G�ran

Elinore wrote:
> i like this 'great' flexibility in FPGA. In this context, i dare to
> make more 'what if' questions (to me, to others)....
> 
> What if we have 2 microblazes (uBLAZE0, uBLAZE1) with  BRAM0 and BRAM1,
> respectively. Suppose BRAM0 ranges 0x00000000 - 0x00003ffff and BRAM1
> ranges 0x00004000 - 0x00007ffff. The uBLAZE0 wanna access BRAM1 using
> shared variable so that programmar see 2 BRAMs as one big global
> memory. Then problem will be bus  ( memory access ) arbitration. So we
> may need a special hardware. Writing an application code will be uneasy
> as well, because we will need only one main routine. How can we utilize
> xilinx-provided design resources to do those? This seems to be very
> hard but interesting ......
> 

hi

Well, in your construction, if two uBLAZEs try to write (or read) to
shared variables at the same time,  what happens?

Another interesting thing will be a programming. In XPS, each processor
has its own main() routine. In case they are communicating with  shared
variables, how can we synchronize  two program ?
By the way, what we want is to do 'one' job (with two processors) !  Is
it possible to run only one main() routine ?
thankyou again for this 'what if' questions

That is standard multi-programming handling.
I would connect two FSL between the two MicroBlazes and let them agree on who 
should use shared resources.

G�ran


Elinore wrote:
> hi
> 
> Well, in your construction, if two uBLAZEs try to write (or read) to
> shared variables at the same time,  what happens?
> 
> Another interesting thing will be a programming. In XPS, each processor
> has its own main() routine. In case they are communicating with  shared
> variables, how can we synchronize  two program ?
> By the way, what we want is to do 'one' job (with two processors) !  Is
> it possible to run only one main() routine ?
> thankyou again for this 'what if' questions
> 

hi

Final --: questions are about the suggestions above- multi-programming
and FSL.
I find FSL is a point2point link in the product specification.
It seems that two approaches are totally different.
Does EDK support such a multi-programming? If yes, in which way? How
can we emulate the shared memory hardware and software (for example,
threaded programming) in Xilinx tool?

2 microblazes with FSL and shared memory ; this looks very exotic and
it seems that we still have two independent main() routines.
In any case, it will be interesting that one main() routine
transperently describe  an algorithm and two microblazes coorperate
each other.

By the way, thankyou very much, G=F6ran

Since both processors starts at address 0, they will start to execute the same 
initialization code.
You need to use a FSL port with different constant signals for each MicroBlaze.
The boot code would then read the FSL port to know which MicroBlaze it's.
Using this it would jump to the right code section.

I would have all code tied on one processor and letting the other processor 
using this as in will start to execute the same program.

Our JTAG debug module handles concurrently up to 8 MicroBlazes in parallel so 
there is no problem debugging this. You will get a gdb window for each MicroBlaze.

It can all be done in the current tools, so just start and have some fun.

G�ran

Elinore wrote:
> hi
> 
> Final --: questions are about the suggestions above- multi-programming
> and FSL.
> I find FSL is a point2point link in the product specification.
> It seems that two approaches are totally different.
> Does EDK support such a multi-programming? If yes, in which way? How
> can we emulate the shared memory hardware and software (for example,
> threaded programming) in Xilinx tool?
> 
> 2 microblazes with FSL and shared memory ; this looks very exotic and
> it seems that we still have two independent main() routines.
> In any case, it will be interesting that one main() routine
> transperently describe  an algorithm and two microblazes coorperate
> each other.
> 
> By the way, thankyou very much, G�ran
>