clock division / multiplication in xilinx cpld

I have a design using a xilinx xc9500xl cpld.  This project is a patch
to an existing project and so not all the signals I need are readily
available.  I have clk/2 and clk*2, but I need clk.  The desired
waveforms are:

clk*2: -.-.-.-.-.-.-.-.
clk:   --..--..--..--..
clk/2: ----....----....

My original, not-well-thought-out plan was to simply take clk*2 and
divide the frequency down simply by toggling an internal signal on
every rising edge of clk*2, and using that as clk.  Easy enough, but
unfortunately half the time this clk ends up out of phase with the
original clk.

clk*2: -.-.-.-.-.-.-.-.
clk:   ..--..--..--..--
clk/2: ----....----....

My next thought was that since I have clk/2 available, I could sync off
of that on the first transition, so that the first rising edge of clk
would occur off of clk/2, which would set an internal "sync" bit, which
would switch a MUX so that clk*2 controller clk as before, but now with
the proper phase.  This relied on having sync and clk internally
initialize to 0.  Xilinx claims this is possible, and simulation works,
but the device is still out of phase half the time.  Any ideas?

Matt

<matthewlawrencecohen@yahoo.com> schrieb im Newsbeitrag
news:1108403870.059404.13360@g14g2000cwa.googlegroups.com...

> I have a design using a xilinx xc9500xl cpld.  This project is a patch
> to an existing project and so not all the signals I need are readily
> available.  I have clk/2 and clk*2, but I need clk.  The desired
> waveforms are:
>
> clk*2: -.-.-.-.-.-.-.-.
> clk:   --..--..--..--..
> clk/2: ----....----....
>
> My original, not-well-thought-out plan was to simply take clk*2 and
> divide the frequency down simply by toggling an internal signal on
> every rising edge of clk*2, and using that as clk.  Easy enough, but
> unfortunately half the time this clk ends up out of phase with the
> original clk.

;-)) Hehe, common pitfall.

> My next thought was that since I have clk/2 available, I could sync off
> of that on the first transition, so that the first rising edge of clk
> would occur off of clk/2, which would set an internal "sync" bit, which

Right way to go.

> would switch a MUX so that clk*2 controller clk as before, but now with
> the proper phase.  This relied on having sync and clk internally
> initialize to 0.  Xilinx claims this is possible, and simulation works,
> but the device is still out of phase half the time.  Any ideas?

Why does a SYNC bit relies on proper initialization?? Its called SYNC, so it
actually measures the signals and then decides what to do. So you need a
real SYNC (tm).
Tried N'Sync ??

;-))

Serious, you have to sample clk/2 using clk*2, maybe on the other edge to
avoid setup/hold problems. Then this sampled clk/2 can be used as a
synchronous reset for your clock divider (ok, its a simple FlipFlop here)

In VHDL it would look like this

process(clk_x2)
begin
  if rising edge(clk_x2) then
     clk_div_2_int <= clk_div2;                -- sample clk/2
     if clk_div_2_int='1' then
       my_divider <= '0';                            -- synchronous reset
     else
       my_divider <= not my_divider;        -- normal clock division
     end if;
  end if;
end process;

clk <= my_divider;

Regards
Falk

<matthewlawrencecohen@yahoo.com> wrote in message
news:1108403870.059404.13360@g14g2000cwa.googlegroups.com...
> I have a design using a xilinx xc9500xl cpld.  This project is a patch
> to an existing project and so not all the signals I need are readily
> available.  I have clk/2 and clk*2, but I need clk.  The desired
> waveforms are:
>
> clk*2: -.-.-.-.-.-.-.-.
> clk:   --..--..--..--..
> clk/2: ----....----....

<snip>

If your timing allows proper sampling of your clk/2 with your clk*2,
register the clk/2 and use the result to determine if you're in phase or
not.

If clkD2^reg_clkD2 (transition just happened) then clk must be 1 (rising
edge just happened)

clk <= ~(clk | (clkD2 ^ reg_clkD2));

matthewlawrencecohen@yahoo.com wrote:
> I have a design using a xilinx xc9500xl cpld.  This project is a patch
> to an existing project and so not all the signals I need are readily
> available.  I have clk/2 and clk*2, but I need clk.  The desired
> waveforms are:
> 
> clk*2: -.-.-.-.-.-.-.-.
> clk:   --..--..--..--..
> clk/2: ----....----....
> 

...

delay clk/2 using clk*2 with a D-FF by one cycle
Then EXOR the original clk/2 and the delayed clk/2
The result should be clk with predictable phase

regards bertram

Bertram has the right idea. But, if you don't like to use an XOR as a
clock source, you can make it an XNOR driving the D input of a
flip-flop clocked by clk*2, and use that Q as the clk output.
Peter Alfke