Hi, Today we released our updated power specs for Stratix II. Some highlights of the updates found in the Stratix II Early Power Estimator V2.1 tool: (1) Reduced static power by up to 47%. We've measured many units from across the product family, and have the data to tighten the spec compared to our previous conservative/estimated values. The amount of change varies from family member to family member, and is a function of junction temperature and whether typical or worst-case silicon is selected. (2) Static current on the VccPD rail now reflected (it is tiny) (3) There is no more in-rush Icc current. The previous current reflected a result measured on early units from one family member plus some excessive guard-bands. The underlying cause was rectified and all Stratix II devices now exhibit a monotonic ramp for Icc and no in-rush. (4) We previously reported around 100 mA of static power per used MRAM in the chip. This turns out to have been a measurement error and now there is no added static power. See http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html for details on the updates and where to get the EPE. Quartus 5.0 will reflect these updated specs when it is released in Q2. Paul Leventis Altera Corp.
Updated Stratix II Power Specs & Explanation
Started by ●February 14, 2005
Reply by ●February 14, 20052005-02-14
Paul, I am delighted. Not only is the static Iccint current > 7.568 amperes at 100C, but the device is clearly doing a thermal runaway (in Excel!). How did you do that? Does the device melt down just like the spreadsheet? It looks as if the solution is iterative, and it keeps trying to converge with the formula for the Iccint being exponetial with T, and the T just getting hotter, and hotter ...) Sure, when the worst case static current is less than the surge, then there is no "surge...." Sure. So if the worst case static is 6 ameres, what is the 'surge' at 25C? Less than 6 amperes, but still there? Smoke and mirrors, mostly smoke? You should really check your spreadsheets before posting. EP2S180, Industrial, Maximum, no air flow, no heat sink, no logic (0 power in the blocks), 36 C ambient (runs away, at 35 C ambient it goes to ~85C. Even a 1/2 degree more causes the Tj to pop to 100+. Now, I admit this is a degenerate case, and people will ususally have some airflow, and maybe even a heatsink. Still ~ 6 amperes just for static current, but at least it won't melt down. At least V4 won't thermally runaway when you turn it on. Austin Paul Leventis wrote:> Hi, > > Today we released our updated power specs for Stratix II. Some > highlights of the updates found in the Stratix II Early Power Estimator > V2.1 tool: > > (1) Reduced static power by up to 47%. We've measured many units from > across the product family, and have the data to tighten the spec > compared to our previous conservative/estimated values. The amount of > change varies from family member to family member, and is a function of > junction temperature and whether typical or worst-case silicon is > selected. > > (2) Static current on the VccPD rail now reflected (it is tiny) > > (3) There is no more in-rush Icc current. The previous current > reflected a result measured on early units from one family member plus > some excessive guard-bands. The underlying cause was rectified and all > Stratix II devices now exhibit a monotonic ramp for Icc and no in-rush. > > (4) We previously reported around 100 mA of static power per used MRAM > in the chip. This turns out to have been a measurement error and now > there is no added static power. > > > See > http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html > for details on the updates and where to get the EPE. Quartus 5.0 will > reflect these updated specs when it is released in Q2. > > > Paul Leventis > Altera Corp. >
Reply by ●February 14, 20052005-02-14
And this post helps the engineering community how? "austin" <austin@xilinx.com> wrote in message news:cur6bv$bag1@cliff.xsj.xilinx.com...> Paul, > > I am delighted. > > Not only is the static Iccint current > 7.568 amperes at 100C, but the > device is clearly doing a thermal runaway (in Excel!). > > How did you do that? Does the device melt down just like the > spreadsheet? It looks as if the solution is iterative, and it keeps > trying to converge with the formula for the Iccint being exponetial with > T, and the T just getting hotter, and hotter ...) > > Sure, when the worst case static current is less than the surge, then > there is no "surge...." > > Sure. So if the worst case static is 6 ameres, what is the 'surge' at > 25C? Less than 6 amperes, but still there? > > Smoke and mirrors, mostly smoke? > > You should really check your spreadsheets before posting. > > EP2S180, Industrial, Maximum, no air flow, no heat sink, no logic (0 > power in the blocks), 36 C ambient (runs away, at 35 C ambient it goes > to ~85C. Even a 1/2 degree more causes the Tj to pop to 100+. > > Now, I admit this is a degenerate case, and people will ususally have > some airflow, and maybe even a heatsink. Still ~ 6 amperes just for > static current, but at least it won't melt down. > > At least V4 won't thermally runaway when you turn it on. > > Austin > > Paul Leventis wrote: > > > Hi, > > > > Today we released our updated power specs for Stratix II. Some > > highlights of the updates found in the Stratix II Early Power Estimator > > V2.1 tool: > > > > (1) Reduced static power by up to 47%. We've measured many units from > > across the product family, and have the data to tighten the spec > > compared to our previous conservative/estimated values. The amount of > > change varies from family member to family member, and is a function of > > junction temperature and whether typical or worst-case silicon is > > selected. > > > > (2) Static current on the VccPD rail now reflected (it is tiny) > > > > (3) There is no more in-rush Icc current. The previous current > > reflected a result measured on early units from one family member plus > > some excessive guard-bands. The underlying cause was rectified and all > > Stratix II devices now exhibit a monotonic ramp for Icc and no in-rush. > > > > (4) We previously reported around 100 mA of static power per used MRAM > > in the chip. This turns out to have been a measurement error and now > > there is no added static power. > > > > > > See > >http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html> > for details on the updates and where to get the EPE. Quartus 5.0 will > > reflect these updated specs when it is released in Q2. > > > > > > Paul Leventis > > Altera Corp. > >
Reply by ●February 14, 20052005-02-14
Well, John, the issue is "what is the leakage current of the new 90nm technology node?". Xilinx has claimed (and we think we have proved it) that the use of triple oxide (basically keeping memory cells and pass gates at 130 nm in 90nm) gives us both speed, and a 3X leakage advantage. Not to mention an SEU advantage (we haven't even started on that weakness in the competition, yet). They claim that their simpler process is more cost effective (? where are the $ quotes ?) and more producable (we are both shipping), and have similar or better leakage, and better speed. These claims are false. Physics is physics. No smoke and mirrors 6 lut is going to work. They may have solved the surge issue, but we have yet to see any parts where that is true. It is also true they do not make it easy for Xilinx to buy their parts. We are oblidged to pay for them like any customer, so there is a fair and level playing field. So we admit we may not have seen their fixed parts. Have you? The engineering community is a group of very well educated professionals who deserve to know what is going on. Most of them have a sense of humor, and appreciate the banter, some do not. If you are one who does not appreciate my postings, please ignore them. If you objected to the tone of my posting, I am very sorry: I can't help it when I see such total nonsense being presented (IMHO). If the gentlemanly thing to do is to respond in a "proper" fashion (in your humble opinion), then I will leave that to others, as I am not going to live long enough to tolerate such nonsense. Life is far too precious to me to waste. Perhaps if you knew me better you would understand. Since you do not, please feel free to ignore me. Again, my intent is to say it like it is, and not to gloss over the fine points, as it is the fine points that leave customers' systems broken and worthless. Let me know what you are objecting to specifically: the truth of the matter, or the tone I take. I can and do apologize, and I am able to learn, grow, and change. austin@xilinx.com Austin PS: from the raw message, I can not see exactly where (or who) you are. I respect that, as I too am inundated with spam, and I understand you wishing to avoid that. John_H wrote:> And this post helps the engineering community how? > > "austin" <austin@xilinx.com> wrote in message > news:cur6bv$bag1@cliff.xsj.xilinx.com... > >>Paul, >> >>I am delighted. >> >>Not only is the static Iccint current > 7.568 amperes at 100C, but the >>device is clearly doing a thermal runaway (in Excel!). >> >>How did you do that? Does the device melt down just like the >>spreadsheet? It looks as if the solution is iterative, and it keeps >>trying to converge with the formula for the Iccint being exponetial with >>T, and the T just getting hotter, and hotter ...) >> >>Sure, when the worst case static current is less than the surge, then >>there is no "surge...." >> >>Sure. So if the worst case static is 6 ameres, what is the 'surge' at >>25C? Less than 6 amperes, but still there? >> >>Smoke and mirrors, mostly smoke? >> >>You should really check your spreadsheets before posting. >> >>EP2S180, Industrial, Maximum, no air flow, no heat sink, no logic (0 >>power in the blocks), 36 C ambient (runs away, at 35 C ambient it goes >>to ~85C. Even a 1/2 degree more causes the Tj to pop to 100+. >> >>Now, I admit this is a degenerate case, and people will ususally have >>some airflow, and maybe even a heatsink. Still ~ 6 amperes just for >>static current, but at least it won't melt down. >> >>At least V4 won't thermally runaway when you turn it on. >> >>Austin >> >>Paul Leventis wrote: >> >> >>>Hi, >>> >>>Today we released our updated power specs for Stratix II. Some >>>highlights of the updates found in the Stratix II Early Power Estimator >>>V2.1 tool: >>> >>>(1) Reduced static power by up to 47%. We've measured many units from >>>across the product family, and have the data to tighten the spec >>>compared to our previous conservative/estimated values. The amount of >>>change varies from family member to family member, and is a function of >>>junction temperature and whether typical or worst-case silicon is >>>selected. >>> >>>(2) Static current on the VccPD rail now reflected (it is tiny) >>> >>>(3) There is no more in-rush Icc current. The previous current >>>reflected a result measured on early units from one family member plus >>>some excessive guard-bands. The underlying cause was rectified and all >>>Stratix II devices now exhibit a monotonic ramp for Icc and no in-rush. >>> >>>(4) We previously reported around 100 mA of static power per used MRAM >>>in the chip. This turns out to have been a measurement error and now >>>there is no added static power. >>> >>> >>>See >>> > > http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.html > >>>for details on the updates and where to get the EPE. Quartus 5.0 will >>>reflect these updated specs when it is released in Q2. >>> >>> >>>Paul Leventis >>>Altera Corp. >>> > > >
Reply by ●February 15, 20052005-02-15
These posts, between Altera and Xilinx, help the engineering community by exposing and discussing critical design-related concerns. People (like me) dig around for any potential problems with parts -- especially the brand new ones (which we always need to use). Although we work very closely with Xilinx on the application of their latest parts, they are not always able and/or willing to disclose *all* of the known issues. Any hint of a potential problem can then be laid out on the table. They are, then, forced to address the issue. Something that may seem benign, to them, may adversely affect our designs. Having these folks jaw at each other, here, is money in the bank, for us. Bob "John_H" <johnhandwork@mail.com> wrote in message news:8TaQd.3$rp4.170@news-west.eli.net...> And this post helps the engineering community how? >> "austin" <austin@xilinx.com> wrote in message > news:cur6bv$bag1@cliff.xsj.xilinx.com... > > Paul, > > > > I am delighted. > > > > Not only is the static Iccint current > 7.568 amperes at 100C, but the > > device is clearly doing a thermal runaway (in Excel!). > > > > How did you do that? Does the device melt down just like the > > spreadsheet? It looks as if the solution is iterative, and it keeps > > trying to converge with the formula for the Iccint being exponetial with > > T, and the T just getting hotter, and hotter ...) > > > > Sure, when the worst case static current is less than the surge, then > > there is no "surge...." > > > > Sure. So if the worst case static is 6 ameres, what is the 'surge' at > > 25C? Less than 6 amperes, but still there? > > > > Smoke and mirrors, mostly smoke? > > > > You should really check your spreadsheets before posting. > > > > EP2S180, Industrial, Maximum, no air flow, no heat sink, no logic (0 > > power in the blocks), 36 C ambient (runs away, at 35 C ambient it goes > > to ~85C. Even a 1/2 degree more causes the Tj to pop to 100+. > > > > Now, I admit this is a degenerate case, and people will ususally have > > some airflow, and maybe even a heatsink. Still ~ 6 amperes just for > > static current, but at least it won't melt down. > > > > At least V4 won't thermally runaway when you turn it on. > > > > Austin > > > > Paul Leventis wrote: > > > > > Hi, > > > > > > Today we released our updated power specs for Stratix II. Some > > > highlights of the updates found in the Stratix II Early PowerEstimator> > > V2.1 tool: > > > > > > (1) Reduced static power by up to 47%. We've measured many units from > > > across the product family, and have the data to tighten the spec > > > compared to our previous conservative/estimated values. The amount of > > > change varies from family member to family member, and is a functionof> > > junction temperature and whether typical or worst-case silicon is > > > selected. > > > > > > (2) Static current on the VccPD rail now reflected (it is tiny) > > > > > > (3) There is no more in-rush Icc current. The previous current > > > reflected a result measured on early units from one family member plus > > > some excessive guard-bands. The underlying cause was rectified andall> > > Stratix II devices now exhibit a monotonic ramp for Icc and noin-rush.> > > > > > (4) We previously reported around 100 mA of static power per used MRAM > > > in the chip. This turns out to have been a measurement error and now > > > there is no added static power. > > > > > > > > > See > > > >http://www.altera.com/corporate/news_room/releases/products/nr-powerplay.htm l> > > for details on the updates and where to get the EPE. Quartus 5.0 will > > > reflect these updated specs when it is released in Q2. > > > > > > > > > Paul Leventis > > > Altera Corp. > > > > >
Reply by ●February 15, 20052005-02-15
"austin" <austin@xilinx.com> wrote in message news:curnam$baj2@cliff.xsj.xilinx.com...> Well, > > John, the issue is "what is the leakage current of the new 90nm technology > node?". > > Xilinx has claimed (and we think we have proved it) that the use of triple > oxide (basically keeping memory cells and pass gates at 130 nm in 90nm) > gives us both speed, and a 3X leakage advantage.Austin, You have posted here that the worst-case silicon, 85 C leakage for Vccint only in an LX200 is 3.3 A. Add to that the 416 mW of Vccaux leakage from the xilinx web power calculator (for typical silicon!) and you get a total *mostly* worst-case silicon, 85 C junction temperature leakage value of 4.38 W. The real worst-case may be higher, since no one from Xilinx has revealed a worst-case Vccaux leakage number. The worst-case silicon, 85 C junction temperature static power for the Stratix II 2S180 is 5.44 W. That number is plainly visible in our Early Power Estimator at http://www.altera.com/support/devices/estimator/st2-estimator/st2_power_est_2.1.xls This means that the Virtex4 leakage is 19.5% lower, with the important caveat that the number is not yet truly worst-case for Virtex4. In any case, hardly 3X. I am amazed that you continue to attack our worst-case silicon power numbers, while Xilinx has not published such numbers for Virtex4. Your customers are going to get themselves into big trouble if they pay attention to your marketing and produce thermal designs for typical leakage, rather than demanding complete power models from Xilinx. If your customers aren't heavily guardbanding their thermal designs, a large part of the silicon you ship them is going to result in operation outside the device thermal specifications. Of course, leakage is the smaller part of the power story. Dynamic power dominates in most designs, and about 65% of dynamic core power in a typical design comes from the logic and routing. According to your web tool, if I instantitate 72,000 slices (half using their FFs, half not) @ 200 MHz, 25% toggle, the dynamic power with medium routing is 9.05 W. We find that a Stratix II ALM implements more logic than a slice. However, even if I ignore that, our web calculator predicts a dynamic power for 72,000 ALMs @ 200 MHz, 25% toggle of 8.449 W. If I take into account the fact that an ALM implements, on average, 11% more logic than a slice, I only need 65,000 ALMs, for a total power of 7.63 W. This results is a small total power advantage for Stratix II: 13.1 W vs. 13.4 W. And I did this comparison at worst-case silicon, 85 C junction temperature, where leakage is the most important! Customers running at cooler temperatures will see leakage being less important. See http://www.altera.com/products/devices/stratix2/features/st2-competitive.html for more data, and some real silicon measurements comparing Virtex4 and Stratix II total power on real designs. Why do we have a dynamic power advantage? Simple: we used a low-k dielectric, as most of the industry has, to increase performance and cut power, while Xilinx did not. Lower k means lower capacitance on all the metal, which is now by far the dominant capacitance. Gives us both a speed and a dynamic power advantage. The last significant component of power is IO power. Here we also measure that we have an advantage, due to having half the pin capacitance of Virtex4. Also gives us a nice signal integrity advantage. Add it all up and you find that Stratix II has a power advantage for high speed designs (lots of dynamic power), while Virtex4 has a power advanage for most low-speed designs with low dynamic & IO power. The power differential is never all that large however, so I expect most customers will make their decisions based on performance, price, and features. Vaughn Betz Altera [v b e t z (at) altera.com]
Reply by ●February 15, 20052005-02-15
Hi Austin,> Not only is the static Iccint current > 7.568 amperes at 100C, butthe> device is clearly doing a thermal runaway (in Excel!).The particular case you point out is not thermal runaway. But with no cooling solution at 36 degrees ambient, the junction temperature will be out of spec (the spreadsheet indicates this with 100+). The reality is that anyone using 180,000 Logic Elements and 1000 I/O pins toggling at a couple hundred Mhz will be dissipitating a lot more dynamic power than static, and a cooling solution of some sort will be necessary irrespective of static power. BTW, we test our chips without heatsinks. They do not go into thermal runway.> It looks as if the solution is iterative, and it keeps > trying to converge with the formula for the Iccint being exponetialwith> T, and the T just getting hotter, and hotter ...)This iteration is a fundamental based on the physics at work here. Static power is made up of a few components, but at 90 nm sub-threshold leakage is the one that dominates. This occurs because transistors aren't really "off". This is especially true on units that come out at the fast end of the process spread (our Worst-Case numbers... you guys don't seem to publish worst-case numbers), since these transistors are leakier (due to lower threshold voltages, narrower channel lengths, etc.). This sub-threshold leakage power increases exponentially with junction (transistor) temperature. But junction temperature (Tj) is a function of overall power dissipation and the cooling solution employed. Cooling solutions (package, thermal compound, heat sink, and air flow) can be represented in the end by a "thermal resistance" expressed in degrees/Watt. This thermal resistance times the total power consumed gives the temperature gradient from Ambient (surrounding air) to the Junction. The parameter used to express this resistance is ThetaJA -- the thermal resistance between junction and ambient. So we have: Power = DynamicPower + StaticPower(Tj) Tj = Ta (ambient) + Power * ThetaJA As you can see, solving for the junction temperature requires iteration. Let's say you've got a chip that burns 1 W of static power @ 25C, and is generating 3W of dynamic power (temperature insensitive). This is a total of 4W at 25C. With no cooling solution, let's say there is a thermal resistance of 10 degrees per Watt between the junction (transistors) and ambient (surrounding air). Let's say the ambient temperature is 25C. Iteration 1: Tj = 25C (ambient) --> Static Power is 1W Iteration 2: Tj = 25C + 4W * 10 deg/Watt = 65C --> Static Power is now (say) 2W Iteration 3: Tj = 25C + 5W * 10 deg/Watt = 75C --> Static Power is now (say) 2.3W Iteration 4: Tj = 25C + 5.3W * 10 deg/Watt = 78C --> Static Power is now 2.4W Iteration 5: Tj = 25C + 5.4W * 10 deg/Watt = 79C --> ... As you can see, we converge on a Tj of ~80C in this hypothetical example. Thermal runaway occurs when the this iteration reaches a point where the incremental amount of static power for a 1 degree change in temperature is greater than the cooling solution's ability to dissipate that power. For example, with a 10 degrees per Watt ThetaJA solution, if we were to ever reach a junction temperature where the Static Power increased by more than .1 W/deg, then the static power would increase faster than we could dissipate and this iteration would result in an infinite junction temperature. In practice, the chip would release the magic smoke that keeps it working.> Sure, when the worst case static current is less than the surge, then> there is no "surge...." > Sure. So if the worst case static is 6 ameres, what is the 'surge'at> 25C? Less than 6 amperes, but still there?At any temperature, worst-case or typical or best-case silicon, there is no surge current. A power supply designed to meet operating conditions will result in succesful device power-up. - Paul
Reply by ●February 15, 20052005-02-15
Paul, nice tutorial. You are a good teacher! But let's look at the so-called reduction of 47% in the Altera leakage current specs: Here is the change in worst-case 85 degree static power (the only static parameter that really matters) from the previous 2.0 to the new 2.1: 2S15 increased (!) by 48 % 2S30 reduced by 1 % 2S60 increased by 4 % 2S90 unchanged 2S130 decreased by 6 % 2S180 decreased by 14 % It takes creative marketing to call that a 47% reduction in leakage current ! Peter Alfke
Reply by ●February 15, 20052005-02-15
Paul, OK. So they do not runaway (in silicon). Should really fix the spreadsheet so it doesn't look like it does. In a similar situation, our web based tool does not "blow up." It will report the actual junction temperature (say 108 C) which will let the designer know that they have exceeded the temp, and also give them an idea by how much they have exceeded the temp. A matter of personal preference perhaps? By stopping all data reporting beyond 100C, you hide the leakage current vs. temperature curve (beyond this point), which makes it harder to see just how bad it can get. At least we show the whole curve. And, as for the surge, the statement you made below is the best description (perhaps the only description) of 'no surge': if the tool says I need X amperes for the design, and I supply X amperes, the design will power on, configure, and work. (Since that is what you clearly said below.) Sincere congratulations on fixing the surge. Our customers have been very happy that we did that six years ago for Virtex II (and kept it out of subsequent product). Austin Paul Leventis wrote:> Hi Austin, > > >>Not only is the static Iccint current > 7.568 amperes at 100C, but > > the > >>device is clearly doing a thermal runaway (in Excel!). > > > The particular case you point out is not thermal runaway. But with no > cooling solution at 36 degrees ambient, the junction temperature will > be out of spec (the spreadsheet indicates this with 100+). The reality > is that anyone using 180,000 Logic Elements and 1000 I/O pins toggling > at a couple hundred Mhz will be dissipitating a lot more dynamic power > than static, and a cooling solution of some sort will be necessary > irrespective of static power. > > BTW, we test our chips without heatsinks. They do not go into thermal > runway. > > >>It looks as if the solution is iterative, and it keeps >>trying to converge with the formula for the Iccint being exponetial > > with > >>T, and the T just getting hotter, and hotter ...) > > > This iteration is a fundamental based on the physics at work here. > Static power is made up of a few components, but at 90 nm sub-threshold > leakage is the one that dominates. This occurs because transistors > aren't really "off". This is especially true on units that come out at > the fast end of the process spread (our Worst-Case numbers... you guys > don't seem to publish worst-case numbers), since these transistors are > leakier (due to lower threshold voltages, narrower channel lengths, > etc.). This sub-threshold leakage power increases exponentially with > junction (transistor) temperature. > > But junction temperature (Tj) is a function of overall power > dissipation and the cooling solution employed. Cooling solutions > (package, thermal compound, heat sink, and air flow) can be represented > in the end by a "thermal resistance" expressed in degrees/Watt. This > thermal resistance times the total power consumed gives the temperature > gradient from Ambient (surrounding air) to the Junction. The parameter > used to express this resistance is ThetaJA -- the thermal resistance > between junction and ambient. > > So we have: > Power = DynamicPower + StaticPower(Tj) > Tj = Ta (ambient) + Power * ThetaJA > > As you can see, solving for the junction temperature requires > iteration. Let's say you've got a chip that burns 1 W of static power > @ 25C, and is generating 3W of dynamic power (temperature insensitive). > This is a total of 4W at 25C. With no cooling solution, let's say > there is a thermal resistance of 10 degrees per Watt between the > junction (transistors) and ambient (surrounding air). Let's say the > ambient temperature is 25C. > > Iteration 1: Tj = 25C (ambient) > --> Static Power is 1W > Iteration 2: Tj = 25C + 4W * 10 deg/Watt = 65C > --> Static Power is now (say) 2W > Iteration 3: Tj = 25C + 5W * 10 deg/Watt = 75C > --> Static Power is now (say) 2.3W > Iteration 4: Tj = 25C + 5.3W * 10 deg/Watt = 78C > --> Static Power is now 2.4W > Iteration 5: Tj = 25C + 5.4W * 10 deg/Watt = 79C > --> ... > > As you can see, we converge on a Tj of ~80C in this hypothetical > example. > > Thermal runaway occurs when the this iteration reaches a point where > the incremental amount of static power for a 1 degree change in > temperature is greater than the cooling solution's ability to dissipate > that power. For example, with a 10 degrees per Watt ThetaJA solution, > if we were to ever reach a junction temperature where the Static Power > increased by more than .1 W/deg, then the static power would increase > faster than we could dissipate and this iteration would result in an > infinite junction temperature. In practice, the chip would release the > magic smoke that keeps it working. > > >>Sure, when the worst case static current is less than the surge, then > > >>there is no "surge...." >>Sure. So if the worst case static is 6 ameres, what is the 'surge' > > at > >>25C? Less than 6 amperes, but still there? > > > At any temperature, worst-case or typical or best-case silicon, there > is no surge current. A power supply designed to meet operating > conditions will result in succesful device power-up. > > - Paul >
Reply by ●February 15, 20052005-02-15
> But let's look at the so-called reduction of 47% in the Alteraleakage> current specs:It was an "up to" number. You should be familiar with these ;-). The biggest change was in the typical specs.> Here is the change in worst-case 85 degree static power (the only > static parameter that really matters)Speaking of which, where are the V-4 worst-case static power numbers? They are the only numbers that matter, but somehow you still haven't published any for V4...> 2S15 increased (!) by 48 % > 2S30 reduced by 1 % > 2S60 increased by 4 % > 2S90 unchanged > 2S130 decreased by 6 % > 2S180 decreased by 14 %Old data was pre-silicon data for many family members. Icc was based on projections. Turns out the curve is flatter than expected, so smaller devices have more current than expected and larger devices have much less current. This is even more evident in the new typical numbers: 25C 85C 2S15 +63% +10% 2S30 -14% -24% 2S60 -17% -19% 2S90 -31% -28% 2S130 -38% -34% 2S180 -38% -38% Now, I think I did my math wrong somewhere in here because I know there is one that decreased by 47%. But you get the idea.> It takes creative marketing to call that a 47% reduction in leakage > current !Righteous indignation from Xilinx for use of an "up to" number? Give me a break. Paul Leventis Altera Corp.