Cyclone clock

Hello,

I have a source of extremely stable and clean clock
signal. Its frequency is about 64 MHz. I would like to
use it as the main clock for a Cyclone FPGA chip
(1C6, to be exact). The problem is that the signal
is a sine wave with the amplitude of about 1Vpp.
The exact level is not an issue, I can amplify or attenuate
it appropriately, but the shape bothers me: may I feed
the FPGA clock input with this signal directly? If yes,
then what is the optimal level of the signal? But if this,
unfortunately, is not allowed, then what solution would
you recommend me?

    Best regards
    Piotr Wyderski

Piotr,

The use of a SSTL input buffer, with a Vref at 1/2 the slicing level (AC 
couple to the input with a bias to Vref) seems to work very well for our 
parts (Xilinx).

I imagine it would work equally well in Altera's parts (with the same IO 
standard and Vref).

The problem with a sine wave is the slow dV/dt.  That will lead to 
jitter when there is ground bounce.

So, for example, if the signal changes 100 ps in 100 mV, then with 100 
mV of ground bounce, I would expect 100 ps of jitter.  More bounce, more 
jitter.  Faster dV/dt, less jitter.  The more dV/dt, the more jitter 
with bounce.  You choose how much clock source jitter you may tolerate.

A separate slicer (comparator) is a better solution in most cases.

Austin


Piotr Wyderski wrote:

> Hello,
> 
> I have a source of extremely stable and clean clock
> signal. Its frequency is about 64 MHz. I would like to
> use it as the main clock for a Cyclone FPGA chip
> (1C6, to be exact). The problem is that the signal
> is a sine wave with the amplitude of about 1Vpp.
> The exact level is not an issue, I can amplify or attenuate
> it appropriately, but the shape bothers me: may I feed
> the FPGA clock input with this signal directly? If yes,
> then what is the optimal level of the signal? But if this,
> unfortunately, is not allowed, then what solution would
> you recommend me?
> 
>     Best regards
>     Piotr Wyderski
> 

"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message 
news:curmki$4pa$1@news.dialog.net.pl...
> Hello,
>
> I have a source of extremely stable and clean clock
> signal. Its frequency is about 64 MHz. I would like to
> use it as the main clock for a Cyclone FPGA chip
> (1C6, to be exact). The problem is that the signal
> is a sine wave with the amplitude of about 1Vpp.
> The exact level is not an issue, I can amplify or attenuate
> it appropriately, but the shape bothers me: may I feed
> the FPGA clock input with this signal directly? If yes,
> then what is the optimal level of the signal? But if this,
> unfortunately, is not allowed, then what solution would
> you recommend me?

You could amplify it with a MMIC (like the MInicircuits ERA-1) and square it 
up with a Schmidt trigger.

Leon 

Leon Heller wrote:

> You could amplify it with a MMIC (like the MInicircuits ERA-1)

The original signal has about 6Vpp and the output is taken from
a divider connected to an emitter follower, so it is enough to
decrease attenuatnion.

> and square it up with a Schmidt trigger.

The problem is that I have no fast enough 3.3V CMOS trigger,
so I decided to use a squaring circuit made of a comparator or
even of discrete elements, like this (at the third picture):

http://www.wenzel.com/documents/waveform.html

    Best regards
    Piotr Wyderski

austin wrote:

> The problem with a sine wave is the slow dV/dt.  That will lead to 
> jitter when there is ground bounce.

Good point, especially taking into account the length
of the clock signal path, which is about 5 cm. 

> A separate slicer (comparator) is a better solution in most cases.

So I will try to find a fast enough comparator or make my
own squaring circuit using two BFR92A UHF transistors.
Thank you for your replies!

    Best regards
    Piotr Wyderski
   

"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message 
news:cusq4p$u8r$1@news.dialog.net.pl...
> Leon Heller wrote:
>
>> You could amplify it with a MMIC (like the MInicircuits ERA-1)
>
> The original signal has about 6Vpp and the output is taken from
> a divider connected to an emitter follower, so it is enough to
> decrease attenuatnion.
>
>> and square it up with a Schmidt trigger.
>
> The problem is that I have no fast enough 3.3V CMOS trigger,
> so I decided to use a squaring circuit made of a comparator or
> even of discrete elements, like this (at the third picture):
>
> http://www.wenzel.com/documents/waveform.html

How about using a couple of diodes to clip the 6V sine signal, and then 
amplify the square wave with a single fast transistor, even easier.

Leon 

"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> schrieb im Newsbeitrag
news:cusq4p$u8r$1@news.dialog.net.pl...

> > and square it up with a Schmidt trigger.
>
> The problem is that I have no fast enough 3.3V CMOS trigger,

What is fast enough?? AFAIK those 74LVC/LVT 14 are quite fast.

Regards
Falk

A limiting amp should make your sine wave much more square.

If limiting amps aren't your thing, a simple external ECL stage cleans up
the clocks quite nicely without the expense of a super-fast comparator since
you can keep the noise introduced into this stage at very low levels,
something you couldn't do with an internal differential input.

"Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message
news:curmki$4pa$1@news.dialog.net.pl...
> Hello,
>
> I have a source of extremely stable and clean clock
> signal. Its frequency is about 64 MHz. I would like to
> use it as the main clock for a Cyclone FPGA chip
> (1C6, to be exact). The problem is that the signal
> is a sine wave with the amplitude of about 1Vpp.
> The exact level is not an issue, I can amplify or attenuate
> it appropriately, but the shape bothers me: may I feed
> the FPGA clock input with this signal directly? If yes,
> then what is the optimal level of the signal? But if this,
> unfortunately, is not allowed, then what solution would
> you recommend me?
>
>     Best regards
>     Piotr Wyderski
>

On Tue, 15 Feb 2005 13:32:21 +0100, "Piotr Wyderski"
<wyderskiREMOVE@ii.uni.wroc.pl> wrote:

>Leon Heller wrote:
>
>> You could amplify it with a MMIC (like the MInicircuits ERA-1)
>
>The original signal has about 6Vpp and the output is taken from
>a divider connected to an emitter follower, so it is enough to
>decrease attenuatnion.

Since the input waveform is a high purity sinewave, there is one point
to be careful about, if that purity is important, e.g. it is a local
oscillator in a radio receiver.

If you are generating very fast edges on a 3V to 5VP-P square wave, it
is very easy to couple a tiny fraction of those edges back onto the
input (through the input buffer and attenuator, through the ground plane
or even through the air) and degrade your LO purity (and interference
rejection) by 40dB or so. 

Careful design (e.g. separate digital and analog ground planes) is
important but even so, a lower edge speed may be better. You will have
to make the right compromise between low jitter (fast edge) and sine
purity, according to the purpose of your design.

- Brian

Brian Drummond wrote:

> Since the input waveform is a high purity sinewave, there is one point
> to be careful about, if that purity is important, e.g. it is a local
> oscillator in a radio receiver.

Yes, it is a very low jitter reference clock for a PLL-based
local oscillator and a strobe of a high-speed ADC (AD6644).

> If you are generating very fast edges on a 3V to 5VP-P square wave, it
> is very easy to couple a tiny fraction of those edges back onto the
> input (through the input buffer and attenuator, through the ground plane
> or even through the air) and degrade your LO purity (and interference
> rejection) by 40dB or so. 

The oscillator is carefully screened, so the only possibility of
coupling is through the power lines. There is a lot of ferrite
beads inside the oscillator box, an LDO and -- finally -- an
active noise canceller, so I think that this way of coupling is
impossible.

    Best regards
    Piotr Wyderski