Xilinx Post Place and Route FIFO problems

Hello All,

Still more problems with FIFOs.  Today I tried to
use the Coregen Wizard to generate a FIFO, hoping
that the generated FIFO would be better than the
one in my previous post.

I clicked on Project, New Source, IP.  Clicked
on Synchronous FIFO, Blocked Memory,
32 Width, 2048 Depth (thinking one BRAM).

I have some extra package that an FAE installed
so I don't know if this is available to the Web Pack
crowd.

I tried to run a Waveform for this generated FIFO
and got a message TestBench Waveforms are not
currently supported for Arch Wizard or CoreGen
sources.

I have seen this problem before and generated a
top level design with the generated FIFO as a
component.  This involves some cut and paste
of the component and instantiation of the VHDL
FIFO code into the top level, basically re copying
the entity ports, the component declaration, and
the instantiation of the FIFO in the top level. You
have to get rid of the word "wrapped".  I'll
put this code at the end.

Same problem however.  The Simulate Behavior
Model runs OK. The Simulate Post-Place and
Route VHDL Model does not.

Brad Smallridge
b r a d @ a i v i s i o n . c o m




library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
 port (
 clk: IN std_logic;
 sinit: IN std_logic;
 din: IN std_logic_VECTOR(31 downto 0);
 wr_en: IN std_logic;
 rd_en: IN std_logic;
 dout: OUT std_logic_VECTOR(31 downto 0);
 full: OUT std_logic;
 empty: OUT std_logic);
end top;

architecture Behavioral of top is

 component fifotest
 port (
 clk: IN std_logic;
 sinit: IN std_logic;
 din: IN std_logic_VECTOR(31 downto 0);
 wr_en: IN std_logic;
 rd_en: IN std_logic;
 dout: OUT std_logic_VECTOR(31 downto 0);
 full: OUT std_logic;
 empty: OUT std_logic);
 end component;


begin

U0 : fifotest
  port map (
   clk => clk,
   sinit => sinit,
   din => din,
   wr_en => wr_en,
   rd_en => rd_en,
   dout => dout,
   full => full,
   empty => empty);

end Behavioral;

Excuse me. Spartan 3 4 BRAMs. 

Brad,
  I've used the Synchronous FIFO's from Coregen, (block ram and distributed) 
and had pretty good success.  ISE6.2 sp3, Modelsim PE5_8 Virtex2, Spartan 
III.  Do you let the ISE projectnav compile all the Modelsim stuff for you 
from the GUI?  It seemed to work OK for me.  Are the FIFO inputs accessed 
directly from the FPGA I/O, and the timing controlled via the testbench? 
Has the Modelsim Resolution been set to "ps"?  Any chance that there is a 
missing process sensitivity item missing?
  It is very difficult to debug a post place and route problem with 
Modelsim.  I feel your pain.

-Newman


"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message 
news:1114apch4l4242c@corp.supernews.com...
> Hello All,
>
> Still more problems with FIFOs.  Today I tried to
> use the Coregen Wizard to generate a FIFO, hoping
> that the generated FIFO would be better than the
> one in my previous post.
>
> I clicked on Project, New Source, IP.  Clicked
> on Synchronous FIFO, Blocked Memory,
> 32 Width, 2048 Depth (thinking one BRAM).
>
> I have some extra package that an FAE installed
> so I don't know if this is available to the Web Pack
> crowd.
>
> I tried to run a Waveform for this generated FIFO
> and got a message TestBench Waveforms are not
> currently supported for Arch Wizard or CoreGen
> sources.
>
> I have seen this problem before and generated a
> top level design with the generated FIFO as a
> component.  This involves some cut and paste
> of the component and instantiation of the VHDL
> FIFO code into the top level, basically re copying
> the entity ports, the component declaration, and
> the instantiation of the FIFO in the top level. You
> have to get rid of the word "wrapped".  I'll
> put this code at the end.
>
> Same problem however.  The Simulate Behavior
> Model runs OK. The Simulate Post-Place and
> Route VHDL Model does not.
>
> Brad Smallridge
> b r a d @ a i v i s i o n . c o m
>
>
>
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> --  Uncomment the following lines to use the declarations that are
> --  provided for instantiating Xilinx primitive components.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity top is
> port (
> clk: IN std_logic;
> sinit: IN std_logic;
> din: IN std_logic_VECTOR(31 downto 0);
> wr_en: IN std_logic;
> rd_en: IN std_logic;
> dout: OUT std_logic_VECTOR(31 downto 0);
> full: OUT std_logic;
> empty: OUT std_logic);
> end top;
>
> architecture Behavioral of top is
>
> component fifotest
> port (
> clk: IN std_logic;
> sinit: IN std_logic;
> din: IN std_logic_VECTOR(31 downto 0);
> wr_en: IN std_logic;
> rd_en: IN std_logic;
> dout: OUT std_logic_VECTOR(31 downto 0);
> full: OUT std_logic;
> empty: OUT std_logic);
> end component;
>
>
> begin
>
> U0 : fifotest
>  port map (
>   clk => clk,
>   sinit => sinit,
>   din => din,
>   wr_en => wr_en,
>   rd_en => rd_en,
>   dout => dout,
>   full => full,
>   empty => empty);
>
> end Behavioral;
>
>
> 

Brad, a synchronous FIFO design ( same clock for write and read)
implemented in a Xilinx dual-ported BlockRAM is really trivial: Two
binary counters and a comparator plus a simple circuit to distinguish
between FULL and EMPTY. Even the partial full calculations can easily
be done in binary.
I would design your FIFO as four parallel BlockRAMs, each 8 bit wide.
BTW, you never mentioned the clock rate.
All the difficulty and trickiness of FIFO design comes when the two
clocks are asynchronous, and you need Gray counters etc.
Peter Alfke, Xilinx Applications

Trivial for you perhaps. But I have done two designs now with
the same problem.  They model OK under Behavior models but
the Post Place and Route Models do not work.

The Clock Rate is a good question.  Going back to the Waveform
and clicking on the Rescale Timing button, I get these numbers:

Clock High Time 10ns
Clock Low Time 10ns
Input Setup Time 5ns
Output Valid Delay 5ns
Offset  0ns

If there is any documentation about what these all mean please point it
out to me.  The only thing I understand fully is the Clock High and
Clock Low times.  50MHz is close to my target application.
My devices are Spartan 3s.

Brad Smallridge
b r a d @ a i v i s i o n . c o m

> Do you let the ISE projectnav compile all the Modelsim stuff for you from 
> the GUI?

YES.

>  Are the FIFO inputs accessed directly from the FPGA I/O, and the timing 
> controlled via the testbench?

YES. Well, as much as my previous post suggest with a Top level module.

> Has the Modelsim Resolution been set to "ps"?

AHA!  It was set to ns, which I guess is the default, but for grins I set it 
for us
and voila! the post place and route does work.  Apparently there are some
setups in there that take longer than 5ns.  Why I didn't see any Warnings 
baffles
me because I was getting them when my settings were at the default 2ns 
setup.

Thank you. Thank you.

> Any chance that there is a missing process sensitivity item missing?

Would that not effect the Behavior model as well?

>  It is very difficult to debug a post place and route problem with 
> Modelsim.  I feel your pain.

What is the best software for post place and route problems?

Thanks again,

Brad Smallridge
b r a d @ a i v i s i o n . c o m

"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message 
news:1114hkl50qr0gc0@corp.supernews.com...
>> Do you let the ISE projectnav compile all the Modelsim stuff for you from 
>> the GUI?
>
> YES.
>
>>  Are the FIFO inputs accessed directly from the FPGA I/O, and the timing 
>> controlled via the testbench?
>
> YES. Well, as much as my previous post suggest with a Top level module.
>
>> Has the Modelsim Resolution been set to "ps"?
>
> AHA!  It was set to ns, which I guess is the default, but for grins I set 
> it for us
> and voila! the post place and route does work.  Apparently there are some
> setups in there that take longer than 5ns.  Why I didn't see any Warnings 
> baffles
> me because I was getting them when my settings were at the default 2ns 
> setup.

I would think that you only get warnings when the data transition falls 
within the setup_hold window.

>
> Thank you. Thank you.
>
>> Any chance that there is a missing process sensitivity item missing?
>
> Would that not effect the Behavior model as well?

Typically, the synthesis tool will issue a warning, and insert the missing 
item in the sensitivity list.
This results in a mismatch between the behaverial and post place and route 
sims.  I believe this to be my number one reason why my simulations 
mismatch.

>
>>  It is very difficult to debug a post place and route problem with 
>> Modelsim.  I feel your pain.
>
> What is the best software for post place and route problems?

Perhaps the dataflow option from Modelsim.  I'm too cheap to buy it, so I 
cannot tell you much about it.

>
> Thanks again,
>
> Brad Smallridge
> b r a d @ a i v i s i o n . c o m
>
> 

"Brad Smallridge" <bradsmallridge@dslextreme.com> schrieb im Newsbeitrag
news:1114hkl50qr0gc0@corp.supernews.com...

> What is the best software for post place and route problems?

NO Post P&R Sim.

If you have a clean synchronous design, just run a Behavioral sim and let
the static timing analyzer see if you hit the desired clock frequency or
not. No hazzle with Post P&R Sim.

Regards
Falk

"newman5382" <newman5382@yahoo.com> schrieb im Newsbeitrag
news:uRrQd.43626$pc5.36254@tornado.tampabay.rr.com...

> >> Any chance that there is a missing process sensitivity item missing?
> >
> > Would that not effect the Behavior model as well?
>
> Typically, the synthesis tool will issue a warning, and insert the missing
> item in the sensitivity list.

Yes, the  synthesizer will do so, but NOT Modelsim. If something is missing
in the sensitivity list you will get funky results :-0

Regards
Falk

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message 
news:37f40gF5cje20U1@individual.net...
> "Brad Smallridge" <bradsmallridge@dslextreme.com> schrieb im Newsbeitrag
> news:1114hkl50qr0gc0@corp.supernews.com...
>
>> What is the best software for post place and route problems?
>
> NO Post P&R Sim.
>
> If you have a clean synchronous design, just run a Behavioral sim and let
> the static timing analyzer see if you hit the desired clock frequency or
> not. No hazzle with Post P&R Sim.
>
> Regards
> Falk
>

Falk,

  When I do my behavioral testbenches, I fashion it so I can do a quicky 
post place and route sanity check of the results against the behavioral 
simulation.  Most of the time, the results match, and all it cost me was 
running a simulation overnight.  I was involved with one design that had a 
Coregen  Async FIFO. One side interfaced with a state machine where the 
timing analyzer said everything was OK, but did not simulate correctly with 
a DCM FX clock multiplication value of 3, but sim'd OK with a value of 2. . 
Also, if the design has multi cycle delay constaints, it might be prudent to 
cross check it against a post place and route simulation.

  To each his own.  I know one guy that does not even do a behavioral 
simulation. He says he might do a visual recheck of his HDL design a second 
time if he is burning it into an OTP part, and he rarely makes a mistake.

-Regards

Newman