DNL and INL calculation

Hi everybody,

Has anyone done DNL and INL calculation using an FPGA yet? Basically I have an 8 bits ramp coming in and I need to calculate DNL and INL.

Thanks, AL

Since FPGAs aren't precise analog devices, what are you expecting the FPGA
to do?

"AL" <ann.lai@analog.com> wrote in message news:ee8be82.-1@webx.sUN8CHnE...
> Hi everybody,
>
> Has anyone done DNL and INL calculation using an FPGA yet? Basically I
have an 8 bits ramp coming in and I need to calculate DNL and INL.
>
> Thanks, AL

I want it to sample these data coming in and then store the data to different bins, i.e. there are data somewhere from 0 to 255 going into the FPGA, the FPGA reads this data and increase the bin count, for example, the FPGA sees 3 coming in, so bin3 count= 1, then a 10 comes in, bin10 count = 1, then 3 comes in, so bin3 count = 2, etc....

Hi,

I don't think you will have a problem with the binning.  Assuming this is for
an ADC digital capture the calculations get a bit more complex. 

For the simple bin count (histogram) using the digital reading to address a
specific counter (one of 255) and just increment the counter currently
addressed should be a quick FPGA design.  
At best I think this would give you a missing codes test.  For INL and DNL
you need to capture more information and sequence is important. 
(monotonicity etc. are part of the typical INL/DNL test)  

You may need to capture the digital codes to memory and depending on the
input signal (different methods could use a ramp, sine, or other input
signal) processes the result.  If the input is a ramp from a DAC then there
is a fair amount of work to interpolate the DAC steps vs the ADC reading to
get a good INL/DNL result (minimize the quantization error.)

Have fun,
    Bart


On Thu, 17 Feb 2005 15:45:38 -0800, AL wrote:

>
>
>I want it to sample these data coming in and then store the data to different bins, i.e. there are data somewhere from 0 to 255 going into the FPGA, the FPGA reads this data and increase the bin count, for example, the FPGA sees 3 coming in, so bin3 count= 1, then a 10 comes in, bin10 count = 1, then 3 comes in, so bin3 count = 2, etc....

Hi, I am sending an 8 bit ramp to the FPGA, this intepolation stuffs, does anyone have example code or application notes or something or does Spartan3 have this function built in somewhere? Thanks, Ann

AL wrote:

> Hi, I am sending an 8 bit ramp to the FPGA, this intepolation stuffs, does anyone have example code or application notes or something or does Spartan3 have this function built in somewhere? Thanks, Ann

You will need to be clearer.
You _do_ have an external Analog To Digital converter, which you are 
trying to test ?

The FPGA itself has NO ADC features, so DNL and INL are meaningless 
applied to a specific FPGA - but you can build an ADC using the FPGA for 
the Digital portions :

** Sigma-Delta ADC with the simple integrator/charge balance/Vref 
devices external
** Successive approximation, needs external Vref, DAC + comparitor
** Fast Tracking ADC - needs external Vref, DAC + comparitor
** Slow Tracking ADC, can use a PWM output, and low pass filter + compatitor

If you want to test an ADC, the simplest way is to wire a better one
in parallel. That way, you can specfiy fractional values for INL and 
DNL. You might also want to specify SFDR - look at other ADC specs.

If your ADC is very high spec, and you cannot find a better one, then
you can use a DAC, or use a PWM DAC in the FPGA, to generate ramps down
to the analog noise floor, and use that to verify your ADC.

-jg

Hi, This is the flow of my board. FPGA -> transmitter -> back to FPGA. So the FPGA generates a ramp and sends to the transmitter, the transmitter transmit the ramp back to the FPGA, we are doing this to test the transmitter. So what kind of ADC do I need to build? I am new at this DNL and INL stuffs. The ramp is just 8 bits 0 to 255 generated by an 8 bit counter. Thanks, Ann

Hi again,

Is this just to test the function of the transmitter/reciever? Bit error rate
might be a better measurement for what you are testing.  If so I might
suggest a simple Psudo Random Pattern Generator with the same PRPG on the
reciever.  You can build this in the FPGA with fairly simple logic and it
will give you a quick data error rate measurement.  Use the first data byte
received as the initial load for the PRPG receiver and then just count the
number of bytes received and the number of miscompares.  Your system error
rate is simply the bad samples / total samples.  You could fix the total
samples to make the math easy and just count the number of failing samples.

  FPGA PRPG source --> Transmitter --> Receiver --> FPGA PRPG compare and
count mismatches

Load the starting seed into the source PRPG and shift through the pattern as
many times as you need for your fail rate calculation.

On the transmit side:
1. Load initial seed
2. Transmit sample
3. Shift PRPG
4. Jump to step 2

On the receive side:
1.  Wait for first sample
2.  Load first sample into the PRPG seed
3.  Shift PRPG
3.  Wait for next sample
4.  Compare sample to PRPG current state
5.  Inc fail count if mismatch
6.  Jump to step 3

The only drawback is if the first sample is bad all the following samples
will fail.  You could get fancy and reload the seed on the receiver if some
number of samples fail in a sucession.

Expect to cycle through a few million samples depending on your transmitter
speed and requirements.  For some devices we look for bit error rate in the
1e10 range (<10 fails in 1e10 samples.)  statisticly we try to run until you
get at least 100 fails.  This may be done with and without any error
correcting (ECC) you might be using to check the raw vs corrected results.


Would something like this do what you are looking for?

  +Bart

On Fri, 18 Feb 2005 14:11:08 -0800, AL wrote:

>
>
>Hi, This is the flow of my board. FPGA -> transmitter -> back to FPGA. So the FPGA generates a ramp and sends to the transmitter, the transmitter transmit the ramp back to the FPGA, we are doing this to test the transmitter. So what kind of ADC do I need to build? I am new at this DNL and INL stuffs. The ramp is just 8 bits 0 to 255 generated by an 8 bit counter. Thanks, Ann

Hi, Thanks Bart for that answer. Yeah that's actually what I am working on right now, and stuck on one part, how do you know when it fail, and how do you know what the bit error rate is? In simulation I can see everything, but when I actually download the code to the FPGA, I don't know what's going on in there. I tried reading the result back via JTAG register, but it didn't work, BSCAN JTAG only allows me to read back register with very simple program. With a program this complicated, it didn't work. In addition to this bit error rate measurement, my boss wants a DNL and INL measurement; so as soon as I get done with this bit error rate measurement, I have to work on the DNL and INL part. Greatly appreciate if anyone can help! Thanks, Ann

On Sat, 19 Feb 2005 21:46:46 -0800, AL wrote:

>
>
>Hi, Thanks Bart for that answer. Yeah that's actually what I am working on right now, and stuck on one part, how do you know when it fail, and how do you know what the bit error rate is? In simulation I can see everything, but when I actually download the code to the FPGA, I don't know what's going on in there. I tried reading the result back via JTAG register, but it didn't work, BSCAN JTAG only allows me to read back register with very simple program. With a program this complicated, it didn't work. In addition to this bit error rate measurement, my boss wants a DNL and INL measurement; so as soon as I get done with this bit error rate measurement, I have to work on the DNL and INL part. Greatly appreciate if anyone can help! Thanks, Ann
<

The bit error rate measurement is fairly simple once you have the transmit
and receive blocks with a compare.  Build a counter large enough for your
fail count (with an overflow indication in case it exceeds your expected fail
count) increment the counter on every miscompare.  Wire the counter output to
a register that you could read with your JTAG interface and read the fail
count.  The bit error rate is simply the ratio of the number of bad compares
to the number of bits transmitted.  There are some variations to the
calculation if you want log error rate etc but it should be a quick
calculation.  If you are having trouble reading out the result you could
build a serial or parallel interface of your choosing to the PC.  Something
like SPI,  I2C, 4 bit parallel (or just wire out to a bunch of 7 segment
displays.)  I have had good results building a serial 3 wire custom SPI
interface on the FPGA and using the PC printer port to clock the FPGA
register bits out.

For your INL and DNL measurements I am not sure where they would fit in with
what I understand about your project.  From the work I have done with INL and
DNL measurements there is usually a DAC or an ADC that is the subject of the
measurement.  If you can give some more details about the functional blocks
you are trying to test I might be able to propose a few options.

Regards,
   Bart