binary constant divider theory

Hi all,

I have two questions:

1. I implemented a binary constant divider in VHDL with my fixed
   point number system.The constant is 0.5. Its signed(1,7). one
   bit for the sign and the rest seven bits for the fraction part.
   All my values are
   between (1,-1). My divider works fine but my question is WHY
   does it work fine? It may sound funny but I dont fully
   understand the theory behind it. I just saw a pattern in
   calculations and wrote my code in VHDL. please help/advise?

ENTITY divider is
  PORT(    a  : IN  unsigned(7 DOWNTO 0);
           o  : OUT unsigned(7 DOWNTO 0));
END divider;
ARCHITECTURE behavior OF divider IS
BEGIN
o(7)<= a(7);
o(6)<= a(5);
o(5)<= a(4);
o(4)<= a(3);
o(3)<= a(2);
o(2)<= a(1);
o(1)<= a(0);
o(0)<= not a(6);
END behavior;



2. Whats the best way to get to know the combinational delay while
using the free Xilinx WebPack tool? When we
   synthesize the design, the synthesis report does give a "Maximum
combinational path delay ". Is that what I should
   be looking at or is it just an estimate??

Thanks in advance
Sourabh

Hi SD u can do the timing analysis for ur design using Xilinx's Timing Analyzer. This tool gives a detailed description about the critical path covered on ur design.

Sourabh,

it seems that you are actually performing a multiplication by 2 ( x / 0.5 = 
x * 2) and so the sign remains the same band the other bits are one position 
left shifted. to me it seems that your module should not give proper result 
if a(6) = 1 and even the value of o(0) should be always zero but this 
happens only if a(6) = 0... so now i am a bit confused...

does it give any clue?

andrea

For simple multiplications and divisions:

X << m    =   X * (2^m)
X >> m    =   X / (2^m)

Be sure not to lose the sign bit on multiplications (i.e. overflow).

Looks like you're trying to do X >>2 i.e. a multiplication by  2
(but the  o(0)<= not a(6) doesn't make any sense).

You don't need to synthesize something this simple to
get an idea of the combinatorial delay.   If you draw this
out you'll see that the prop delay is simply a wire between
two flops.

My advice to you would be to first understand what you're trying
to do before coding it up and synthesizing.  There are
no shortcuts.

-Paul

Paul wrote:
> For simple multiplications and divisions:
>
> X << m    =   X * (2^m)
> X >> m    =   X / (2^m)
>
> Be sure not to lose the sign bit on multiplications (i.e. overflow).
>
> Looks like you're trying to do X >>2 i.e. a multiplication by  2
> (but the  o(0)<= not a(6) doesn't make any sense).
>
> You don't need to synthesize something this simple to
> get an idea of the combinatorial delay.   If you draw this
> out you'll see that the prop delay is simply a wire between
> two flops.
>
> My advice to you would be to first understand what you're trying
> to do before coding it up and synthesizing.  There are
> no shortcuts.
>
> -Paul

Paul,

My second question was a general question about combination delay, not
specific to the design we are looking at. Yes, I think theres a fix I
need to make in this code. I would apprecu=iate if you could aadvise on
the combination delay question/

Thanks

y <= x  is a wire assignment; there is no logic in the path.

Your combinatorial delay is the of the actual wire on the chip,
with all the routing switchbox overhead.  Read the Altera or
Xilinx device reference manual section which explains the
circuit architecture of the chip you're using to gain an understanding
of what you're mapping to.

Paul

Paul wrote:
> y <= x  is a wire assignment; there is no logic in the path.
>
> Your combinatorial delay is the of the actual wire on the chip,
> with all the routing switchbox overhead.  Read the Altera or
> Xilinx device reference manual section which explains the
> circuit architecture of the chip you're using to gain an
understanding
> of what you're mapping to.
>
> Paul



Paul,

I guess I'm really bad at expressing myself. Ok so heres one last try
of explaining my question.
Lets say I do have a design which involves lot of logic (multipliers,
adders, subtractors etc etc). My question is whats the best way to find
out the exact delay using free Xilinx WebPack? the synthesis report
does give me a max combination path delay, is that what I should be
looking at?

Thanks in advance.

"SD" <sourabh.dhir@gmail.com> schrieb im Newsbeitrag
news:1108668502.344775.89450@c13g2000cwb.googlegroups.com...

> adders, subtractors etc etc). My question is whats the best way to find
> out the exact delay using free Xilinx WebPack? the synthesis report
> does give me a max combination path delay, is that what I should be
> looking at?

Sythesis reoprt is just a rough estimate, often ways wrong. What you need is
the timing report after Place & Route. If you set some timing constrainst in
your UCF, the timing analyzer will check those and write out a report if the
deign meets your requirement or not. A simple timing constaint is

NET my_clock period = 10ns;

This tells the timing analyzer checks if the logic between your FlipFlops
need less than 10 ns propagation delay (including clock2out and setup
times).
There are much more timing constraints, but this is getting more complex.

Regards
Falk

Falk,

Thanks for the input. What if my design is a pure combination logic
(unregistered), I mean no clocks. So now whatever the synthesis report
gives me, is it still way off the mark??

"SD" <sourabh.dhir@gmail.com> schrieb im Newsbeitrag
news:1108700783.719360.228940@l41g2000cwc.googlegroups.com...
> Falk,
>
> Thanks for the input. What if my design is a pure combination logic
> (unregistered), I mean no clocks. So now whatever the synthesis report
> gives me, is it still way off the mark??

More or less. The problem is, that the timing analyzys after synthesis has
no clue about placement and routing. Yes, it can estimate an average
placement/routing delay, but this is still not really a valueable number. If
you want to know the propagation delay of your logic, use timing constaints
like

TIMESPEC "TS_my_delay"  = FROM PADS TO PADS 20ns;

This will tell te timing analyzer that you  need a combinatorical delay of
20ns or less from all input pads to all output pads.
You can also have a look into the asynchrounous delay report, it listas all
net delays. But can be tricky in a big design.

Regards
Falk