Shift register example? Hi I am looking for a parallel in serial out latching shift register in VHDL. I want 16 bits but any example would be appreciated. Thanks
Shift register example?
Started by ●February 18, 2005
Reply by ●February 19, 20052005-02-19
probably something like
---------------------------------
signal cpt : integer range 0 to 15; --i'm not sure for this declaration
usually i use only std_logic with convertion
signal temp : std_logic_vector( 15 downto 0);
process(clk)
begin
if rising_edge(clk) then
cpt <= cpt +1 ;
if cpt = 0 then
temp <= in_parallel;
end if;
out_serie <= temp(cpt);
end if;
end process;
----------------------------------------
there is many others way to do it you just have to test different solution
to get the better and have imagination...
alexis
"bob" <kmart@nospam.com> a �crit dans le message de news:
jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com...
> Shift register example?
> Hi I am looking for a parallel in serial out latching shift register
> in VHDL.
> I want 16 bits but any example would be appreciated.
>
> Thanks
>
Reply by ●February 20, 20052005-02-20
Well, there are some issues with this code example: 1) The reset is missing, this is a problem for the simulation 2) integer based counters tend to not wrap arount automatically, I do not know for sure what synthesis might result, but simulation will fail 3) While the general behavior is ok with the above points corrected, this is not a shift register. Sorry. See notes below. Try again! Chris KCL wrote:> probably something like > --------------------------------- > signal cpt : integer range 0 to 15; --i'm not sure for this declarationthis is ok> usually i use only std_logic with convertion > signal temp : std_logic_vector( 15 downto 0); > > process(clk) > beginMissing reset here, initialize cpt here!> if rising_edge(clk) then > cpt <= cpt +1 ;This is a counter which does not wrap around, since it is of type integer! Take care!> if cpt = 0 then > temp <= in_parallel; > end if;Parallel loadable register. ok.> out_serie <= temp(cpt);Multiplexer, with output register. NOT a shift register!! Where is the shift??> end if; > end process; > ---------------------------------------- > > > there is many others way to do it you just have to test different solution > to get the better and have imagination... > > alexis > > "bob" <kmart@nospam.com> a �crit dans le message de news: > jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com... > >>Shift register example? >>Hi I am looking for a parallel in serial out latching shift register >>in VHDL. >>I want 16 bits but any example would be appreciated. >> >>Thanks >> > > >
Reply by ●February 20, 20052005-02-20
thanks for note 1) integer count : usually i use std_logic for all my signal and use conversion function for arithmetic, so i have no problem of wrap around, 2) reset missing : does at startup all signal have a value unknow but equal to '1' or '0' so after max 16cycles cpt should back to 0 so there is a 16 cycle clock intial time that (depend of your application need but in most of DSP) is not important I think. Also for reset what is the best synchronous or asynchronous?? because synchronous reset seems to need less ressource?? 3)not a shift register but i think this not a real shift register he wanted :"parallel in serial out latching shift register" for me he asked for serializator (sorry my english is so bad so I translate as I can) if i wanted to do a shift register i will have done: data_reg <= data_reg(14 downto 0) & data_in; data_out <= data_reg(0); Finally I just will add that still people not explain very well what they wanted , we couldn't give them exactely what they want to do (and also that they could search by themself , it 's not not too bad for brain activity) And excuse me for my "errors" but I just notice that only a french guy with only 6month internship in VHDL developpement(and limited english comprehension) take time to answer to his problem. Regards Alexis "Christian Schneider" <please_reply_to_the@newsgroup.net> a �crit dans le message de news: cv9vne$3ua$1@online.de...> Well, there are some issues with this code example: > > 1) The reset is missing, this is a problem for the simulation > > 2) integer based counters tend to not wrap arount automatically, I do not > know for sure what synthesis might result, but simulation will fail > > 3) While the general behavior is ok with the above points corrected, this > is not a shift register. Sorry. See notes below. > > Try again! > Chris > > > KCL wrote: >> probably something like >> --------------------------------- >> signal cpt : integer range 0 to 15; --i'm not sure for this declaration > this is ok > >> usually i use only std_logic with convertion >> signal temp : std_logic_vector( 15 downto 0); >> >> process(clk) >> begin > > Missing reset here, initialize cpt here! > >> if rising_edge(clk) then >> cpt <= cpt +1 ; > This is a counter which does not wrap around, since it is of type integer! > Take care! > >> if cpt = 0 then >> temp <= in_parallel; >> end if; > Parallel loadable register. ok. > >> out_serie <= temp(cpt); > Multiplexer, with output register. NOT a shift register!! Where is the > shift?? > >> end if; >> end process; >> ---------------------------------------- >> >> >> there is many others way to do it you just have to test different >> solution to get the better and have imagination... >> >> alexis >> >> "bob" <kmart@nospam.com> a �crit dans le message de news: >> jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com... >> >>>Shift register example? >>>Hi I am looking for a parallel in serial out latching shift register >>>in VHDL. >>>I want 16 bits but any example would be appreciated. >>> >>>Thanks >>> >> >>
Reply by ●February 20, 20052005-02-20
I made a mistake shift register is :> data_reg <= data_in & data_reg(14 downto 0) ; > data_out <= data_reg(0);"KCL" <kclo4_NO_SPAM_@free.fr> a �crit dans le message de news: 4218ad31$0$6618$8fcfb975@news.wanadoo.fr...> thanks for note > > > 1) integer count : usually i use std_logic for all my signal and use > conversion function for arithmetic, so i have no problem of wrap around, > > 2) reset missing : does at startup all signal have a value unknow but > equal to '1' or '0' so after max 16cycles cpt should back to 0 so there > is a 16 cycle clock intial time that (depend of your application need but > in most of DSP) is not important I think. > > Also for reset what is the best synchronous or asynchronous?? because > synchronous reset seems to need less ressource?? > > 3)not a shift register but i think this not a real shift register he > wanted :"parallel in serial out latching shift register" for me he asked > for serializator (sorry my english is so bad so I translate as I can) > if i wanted to do a shift register i will have done: > > > data_reg <= data_reg(14 downto 0) & data_in; > data_out <= data_reg(0); > > Finally I just will add that still people not explain very well what they > wanted , we couldn't give them exactely what they want to do (and also > that they could search by themself , it 's not not too bad for brain > activity) > And excuse me for my "errors" but I just notice that only a french guy > with only 6month internship in VHDL developpement(and limited english > comprehension) take time to answer to his problem. > > Regards > > Alexis > > "Christian Schneider" <please_reply_to_the@newsgroup.net> a �crit dans le > message de news: cv9vne$3ua$1@online.de... >> Well, there are some issues with this code example: >> >> 1) The reset is missing, this is a problem for the simulation >> >> 2) integer based counters tend to not wrap arount automatically, I do not >> know for sure what synthesis might result, but simulation will fail >> >> 3) While the general behavior is ok with the above points corrected, this >> is not a shift register. Sorry. See notes below. >> >> Try again! >> Chris >> >> >> KCL wrote: >>> probably something like >>> --------------------------------- >>> signal cpt : integer range 0 to 15; --i'm not sure for this declaration >> this is ok >> >>> usually i use only std_logic with convertion >>> signal temp : std_logic_vector( 15 downto 0); >>> >>> process(clk) >>> begin >> >> Missing reset here, initialize cpt here! >> >>> if rising_edge(clk) then >>> cpt <= cpt +1 ; >> This is a counter which does not wrap around, since it is of type >> integer! Take care! >> >>> if cpt = 0 then >>> temp <= in_parallel; >>> end if; >> Parallel loadable register. ok. >> >>> out_serie <= temp(cpt); >> Multiplexer, with output register. NOT a shift register!! Where is the >> shift?? >> >>> end if; >>> end process; >>> ---------------------------------------- >>> >>> >>> there is many others way to do it you just have to test different >>> solution to get the better and have imagination... >>> >>> alexis >>> >>> "bob" <kmart@nospam.com> a �crit dans le message de news: >>> jgpb11pishb8c3lqkt6s49lo7hhve16674@4ax.com... >>> >>>>Shift register example? >>>>Hi I am looking for a parallel in serial out latching shift register >>>>in VHDL. >>>>I want 16 bits but any example would be appreciated. >>>> >>>>Thanks >>>> >>> >>> >
Reply by ●February 21, 20052005-02-21
KCL wrote:> 1) integer count : usually i use std_logic for all my signal and use > conversion function for arithmetic, so i have no problem of wrap around,That's right.> 2) reset missing : does at startup all signal have a value unknow but equal > to '1' or '0' so after max 16cycles cpt should back to 0 so there is a 16 > cycle clock intial time that (depend of your application need but in most of > DSP) is not important I think.I do not agree with you here: what is "XXXX" + 1 ? I had a lot of simulations which did not start properly because of wrong initial values. Well in hardware all would work, but your simulation still differs in behaviour. This is mainly because hardware does not have the "XXXX" value. Since we are here in the FPGA news group, all FPGAs I know of initialize with zero, unless other values are set.> Also for reset what is the best synchronous or asynchronous?? because > synchronous reset seems to need less ressource??I have read a lot about resets in this newsgroup and I really do not understand why so few people use the "reset on configuration": When you download the bitstream everything has its default, so what else do you want? You can just program it as asynchronous reset and the tools do the rest (nearly).> 3)not a shift register but i think this not a real shift register he wanted > :"parallel in serial out latching shift register" for me he asked for > serializator (sorry my english is so bad so I translate as I can) > if i wanted to do a shift register i will have done: > > > data_reg <= data_reg(14 downto 0) & data_in; > data_out <= data_reg(0);A shift register would have been much faster, and uses much less logic resources.> Finally I just will add that still people not explain very well what they > wanted , we couldn't give them exactely what they want to do (and also that > they could search by themself , it 's not not too bad for brain activity) > And excuse me for my "errors" but I just notice that only a french guy with > only 6month internship in VHDL developpement(and limited english > comprehension) take time to answer to his problem.Yes you are right, the task is not completely mentioned. I just wanted to correct the source code, sorry for the harsh tone. Best regards, Chris
Reply by ●February 21, 20052005-02-21
Hi FYI
I found this on the web and it is the same part that I use when I do
this with hardware.
However like the real part there is no reset. Do you think that the
lack of reset condition will cause problems other than simulation with
an unknown initial condition on the serial output pin?
As for the use it is to impliment a simple SPI output of a 16 bit
counter that I had sent to a seven segment decoder than an lcd but now
want to transfer into my PC.
Thanks
--
-- ls165.vhd
--
-- Description: This is a VHDL synthesizable description of the
74LS165
-- 8-Bit Parallel-to-Serial Shift Register.
--
--
-- Author: Wilson Li
-- Date: March 27, 1997
--
--
library ieee;
use ieee.std_logic_1164.all;
entity ls165 is
port(
p: in std_logic_vector(7 downto 0);
pl: in std_logic;
ds: in std_logic;
cp1: in std_logic;
cp2: in std_logic;
q7: out std_logic;
q7_bar: out std_logic
);
end ls165;
architecture ls165_body of ls165 is
signal q_buf: std_logic_vector(7 downto 0);
signal gated_clk: std_logic;
begin
q7 <= q_buf(7);
q7_bar <= not q_buf(7);
gated_clk <= cp1 or cp2;
process(gated_clk)
begin
if gated_clk'event and gated_clk = '1' then
if pl = '0' then
q_buf <= p;
else
-- shift by 1 bit
--
q_buf(0) <= ds;
q_buf(1) <= q_buf(0);
q_buf(2) <= q_buf(1);
q_buf(3) <= q_buf(2);
q_buf(4) <= q_buf(3);
q_buf(5) <= q_buf(4);
q_buf(6) <= q_buf(5);
q_buf(7) <= q_buf(6);
end if;
end if;
end process;
end ls165_body;
On Fri, 18 Feb 2005 07:57:10 -0500, bob <kmart@nospam.com> wrote:
>Shift register example?
>Hi I am looking for a parallel in serial out latching shift register
>in VHDL.
>I want 16 bits but any example would be appreciated.
>
>Thanks
Reply by ●February 21, 20052005-02-21
Christian Schneider wrote:>> Also for reset what is the best synchronous or asynchronous?? because >> synchronous reset seems to need less ressource?? > > I have read a lot about resets in this newsgroup and I really do not > understand why so few people use the "reset on configuration": When > you download the bitstream everything has its default, so what else > do you want? You can just program it as asynchronous reset and the > tools do the rest (nearly).The reset on configuration is not guaranteed to be fast enough (in all chips) to bring everything out of reset at the same time. This can cause problems if your code expects this. Xilinx specifically recommends that you not use GSR in the Virtex, at least, because of the amount of skew. In addition - I'm not clear whether asynch. resets are covered by timing analysis. If it's not, then that leads to the same problem. Somebody else might be better equipped to comment on this. Jeremy
Reply by ●February 21, 20052005-02-21
For reset as Chris says if there is no reset you will have problem for simulate There is some problems in the code there is no counter to control the load of the data so you must take care when p is set to 1 (this is the condition for load ) and when the data will have been sent you will send ds signal so be sure of what you wanna sent after your data word and finnally preferably than writing> q_buf(0) <= ds; > q_buf(1) <= q_buf(0); > q_buf(2) <= q_buf(1); > q_buf(3) <= q_buf(2); > q_buf(4) <= q_buf(3); > q_buf(5) <= q_buf(4); > q_buf(6) <= q_buf(5); > q_buf(7) <= q_buf(6);you could write q_buff <= q_buff(6 downto 0 )& ds; that a little bit faster to write ;) Regards alexis "bob" <kmart@nospam.com> a �crit dans le message de news: jjhk119tkkb1vmhv13jeevr5ctup00djs3@4ax.com...> Hi FYI > I found this on the web and it is the same part that I use when I do > this with hardware. > However like the real part there is no reset. Do you think that the > lack of reset condition will cause problems other than simulation with > an unknown initial condition on the serial output pin? > As for the use it is to impliment a simple SPI output of a 16 bit > counter that I had sent to a seven segment decoder than an lcd but now > want to transfer into my PC. > Thanks > > -- > -- ls165.vhd > -- > -- Description: This is a VHDL synthesizable description of the > 74LS165 > -- 8-Bit Parallel-to-Serial Shift Register. > -- > -- > -- Author: Wilson Li > -- Date: March 27, 1997 > -- > -- > > library ieee; > use ieee.std_logic_1164.all; > > > entity ls165 is > port( > p: in std_logic_vector(7 downto 0); > pl: in std_logic; > ds: in std_logic; > cp1: in std_logic; > cp2: in std_logic; > q7: out std_logic; > q7_bar: out std_logic > ); > end ls165; > > > architecture ls165_body of ls165 is > > signal q_buf: std_logic_vector(7 downto 0); > signal gated_clk: std_logic; > > begin > > q7 <= q_buf(7); > q7_bar <= not q_buf(7); > gated_clk <= cp1 or cp2; > > process(gated_clk) > > begin > > if gated_clk'event and gated_clk = '1' then > > if pl = '0' then > > q_buf <= p; > > else > > -- shift by 1 bit > -- > q_buf(0) <= ds; > q_buf(1) <= q_buf(0); > q_buf(2) <= q_buf(1); > q_buf(3) <= q_buf(2); > q_buf(4) <= q_buf(3); > q_buf(5) <= q_buf(4); > q_buf(6) <= q_buf(5); > q_buf(7) <= q_buf(6); > > end if; > > end if; > > end process; > > end ls165_body; > > > > > On Fri, 18 Feb 2005 07:57:10 -0500, bob <kmart@nospam.com> wrote: > >>Shift register example? >>Hi I am looking for a parallel in serial out latching shift register >>in VHDL. >>I want 16 bits but any example would be appreciated. >> >>Thanks >
Reply by ●February 21, 20052005-02-21
> I have read a lot about resets in this newsgroup and I really do not > understand why so few people use the "reset on configuration": When > you download the bitstream everything has its default, so what else > do you want? You can just program it as asynchronous reset and the > tools do the rest (nearly). >So if i use asynchronous reset, all internal signal will be set at the reset value at the startup of the fpga??> A shift register would have been much faster, and uses much less logic > resources.I have check , and I have nothing else to add that you are right, little padawan have a lot to learn^^ I have dl the xilinx synthesis design guide, now let's read it (400p ->thales's guide was smaller... : ~ )> Yes you are right, the task is not completely mentioned. > I just wanted to correct the source code, sorry for the harsh tone. > >No problem for the "the harsh tone", I just have some problem with critics even more actually because I'm tired of those french firm that take no risk with young graduates like me and prefer older engineer without skill. :# Regards Alexis
